RISC-V is an open instruction set architecture (ISA) drafted by the University of California, Berkeley, characterized by streamlining, modularity, and scalability. Its flexible and open architecture features have driven the ecosystem to grow rapidly. After the establishment of the RISC-V Foundation, RISC-V ISA has attracted a lot of attention in the CPU field. At present, many large-scale system companies and IC design companies have joined the RISC-V camp to promote the continued development of RISC-V technology. Thanks to RISC -V's streamlined, scalable architecture, including ADAS, AI, IoT, Networking, Storage and many other emerging hotspots, with its ecosystem of explosive growth potential, its future development is limitless.
With more than ten years of experience in designing low-power, high-performance 32/64-bit processor cores, Crystal Technology has shipped 2.5 billion chips in the embedded AndesCoreTM core. As a founding member of RISC-V The positioning of Jingxin is to bring this rich development experience into the development of RISC-V architecture to lead RISC-V into the mainstream market. For example, Jingxin will develop the instruction set and system architecture advantages of the past with RISC-V. The architecture builds a furnace and builds the RISC-V-compatible crystal core fifth-generation instruction set architecture family AndeStarTM V5. At the 7th RISC-V seminar in Silicon Valley, Jingxin Technology proposed the DSP instruction set as The basis of the RISC-VP-Extended Instruction Set (Packed SIMD), which is derived from the Digital Signal Processor Instruction Set (DSP ISA) of the successful D10 and D15 processors from Crystals Technology. In addition, Crystal Center Actively participate in RISC-V open source software; from compilers, link libraries, debuggers to Linux kernel and other important open source software, Crystal is the main contributor to RISC-V.
The 32-bit AndesCoreTM N25 and the 64-bit AndesCoreTM NX25 are based on the AndeStarTM V5 instruction set. These two powerful and highly configurable RISC-V CPU cores have been released since the fourth quarter of 2017. In the high performance, low power consumption and small area, it has received wide attention and welcome in the industry. Jingxin also provides N25 and NX25SoC platforms, which can pre-integrate the CPU subsystem with the bus matrix and peripheral IP ( Pre-integrated) to simplify the design transfer and integration of design engineers to quickly start SoC design. In order to fully utilize the performance of N25 and NX25, Jingxin also provides highly optimized compiler and fully functional integrated development environment (IDE). To help customers increase the competitiveness of their end products in the shortest time. In addition, in the third quarter of this year, Jingxin plans to continue to launch four RISC-V-based architectures that support floating-point computing and Linux's latest CPU Cores: N25F. A25, NX25F and AX25.
The core RISC-V core has been adopted by Taiwan, China, the United States and other customers, and will continue to expand its alliance with quality design service providers to provide new kinetic energy for rapid development of end-user systems. It achieves the goal of Time to market.