According to the current information of EE Times, Wave Computing's 7nm development plan will use Broadcom Inc.'s ASIC chip design. Wave and Broadcom will use TSMC's 7nm process technology to jointly develop Wave's next-generation data flow processing unit (DPU).
The new 7nm DPU will be provided by Broadcom, but the timetable is undecided. According to Wave CEO Derek Meyer, the 7nm DPU will be 'designed in our own AI system.' He added, 'If other companies in the market have For this requirement, the same chip can also be provided.'
Derek MeyerDerek Meyer market research firm Tirias Research principal analyst Kevin Krewell said, 'Wave hopes to stand out from the startup with this 7nm design. Currently, most startups don't have the expertise and capabilities to build 7nm components. He explained that Wave, with the help of Broadcom, made this possible. He pointed out that Broadcom's acquisition of LSI Logic does have more advanced ASIC circuit design experience.
Wave's current DPU generation is based on a 16nm process design.
'In the industry of designing new AI accelerators, we will be the first to get 7nm physical IP - such as 56Gbps and 112Gbps SerDes, thanks to Broadcom's assistance. ' Meyer pointed out that Broadcom brings advanced design platforms, mass production technology and The proven 7nm IP has helped us implement this 7nm product development plan.
Wave's current DPU generation is based on 16nm process nodes, which is mainly done by Wave's own designers and contractors. As for the 7nm DPU, Meyer said, 'Between Broadcom and Wave, we have developed the 'ASIC' design front end and back. The required technologies and resources have been developed, and a cooperation plan has been developed accordingly.
Currently, this 7nm cooperation plan has been launched and continues for several months. Broadcom will be responsible for the physical part of the 7nm chip. Although the 7nm design is very complicated, Meyer said, 'I believe Broadcom will launch the right chip for the first time. However, Wave did not disclose when its 7nm DPU will be available, nor does it explain the 7nm DPU architecture.
7nm DPU internal disclosure
However, Meyer explained that the new chip will be 'based on the data flow architecture'. It will be the first DPU with a '64-bit (64-bit) MIPS multi-threaded CPU'. Acquired MIPS.
Meyer also pointed out that Wave's 7nm chip will be equipped with new features in memory, but he did not disclose what new features have been added.
However, Meyer said that MIPS' multi-threading technology will play a key role in the new generation of DPUs. Through Wave's data stream processing, 'When we load, unload and reload data for machine learning agents, hardware and more execution The architecture will be very efficient. ' In addition, MIPS's cache coherency will be another important feature of Wave's new DPU. He said, 'Because our DPU is a 64-bit architecture, it is only in MIPS and DPU. It also makes sense to communicate with the same memory in a 64-bit address space. '
For the new features that Wave will add to memory, Krewell said, 'Wave's existing chips use Micron's Hybrid Memory Cube (HMC). And I think Wave's future chips will turn to high-bandwidth memory ( HBM). ' He added: 'HBM's future development blueprint is better. The ever-changing memory architecture will have an impact on the overall system architecture.'
Karl Freund, senior analyst at Moor Insights & Strategy, agrees. He said: 'For the memory part, I guess they will abandon the hybrid memory cube and switch to high-bandwidth memory because it is more cost-effective.'
In an interview, Meyer announced that the new 7nm DPU is expected to provide 10 times higher performance than its existing chips.
He said, 'Don't forget, we have separated the clock in the DPU architecture from the chip before.' He pointed out that moving back and forth between hosts will cause a bottleneck, while in the DPU, the embedded microcontroller can load instructions. , reduce the power and delay of traditional accelerator waste. 'We can effectively play the transistor capacity on the 7nm chip to improve performance.'
However, Krewell has reservations about this. He said: 'As for whether Wave can achieve 10 times performance in terms of performance, this is a long journey, it must be based on how to measure the performance of machine learning... and Derek 'Meyer' It’s talking about training or inference.” He added, “There are many changes in the inferences, and they are also deployed with lower precision (8-bit or lower) algorithms. The performance of training depends mainly on the memory architecture. However, he also admitted, 'I don't really know the details of Wave's calculations.'
Compile: Susan Hong