Prior to the above news, a number of technology giants have indicated that they are RISC-V, including Samsung, NVIDIA, Western Digital (WD), etc., which has paid little attention to the industry, but with the chip more Close to commercial use, attention has begun to increase. Why is the RISC-V instruction set architecture? Why is it gradually supported by technology manufacturers and new entrepreneurs? This article will discuss this discussion below.
Intel/Anmou is a proprietary instruction set architecture
RISC-V is an open source code instruction set architecture. In fact, it used to be called an Instruction Set for a long time in the industry, but it may be added to the architecture in order to make three letters that can be abbreviated (Architecture , A) word.
The instruction set refers to a set of instructions in a bunch of combined languages (the most primitive language on the chip). A set of instructions is composed of a few dozens and hundreds of instructions. If a microcontroller The microprocessor chip can execute the set of instructions, and the other can also support the execution of the same set of instructions. In principle, the software (the software is composed of instructions) does not need any rewriting, and can be freely in two. Replacement between chips.
Similarly, chip vendors are introducing a new generation of better-performing chips that typically use the same instruction set as the previous generation, or are fully compatible but add new instructions to ensure that many of the developed software does not need to be rewritten. Enforcement to protect customers' past software development investments, purchase investments, and execute faster.
Most of the chips currently on the market use Intel or Amim's instruction set architecture. Intel's instruction set architecture is generally called x86 (in the past, it was used for series of chips ending with 86 number, such as 8086, 80286, 80386, 80486, etc.) ), IA (Intel Architecture), IA-32 (32-bit between 1982 and 2003), EM64T (Extended Memory 64 Technology) or AMD64/x86-64/x64 (64-bit version led by AMD AMD) Etc. The conspiracy is directly called the Arm instruction set architecture.
Intel and Arm's instruction set architecture are proprietary architectures designed by the company. They must be paid for use. Intel's ISA must purchase the CPU chips sold by the company. Arm's ISA is indirect sales. The ISA must first pay a one-time technical license fee, and then every time a chip is produced, it will be charged by Arm.
Intel's x86 ISA chips are overwhelmingly dominated in PCs, workstations, servers, supercomputers, etc., so the price is high for a long time, system vendors, end consumers must bear the cost, although a few chip vendors can also produce and sell X86 ISA chip, but the price performance ratio or supply is not as high as Intel, and there are many restrictions, such as AMD can use x86 ISA, but if the company is purchased afterwards, the x86 ISA patent right must be revisited, or other Although chip makers also produce x86 compatible chips, they must pay US royalties to IBM to avoid Intel's possible lawsuits.
On the Arm side, Arm's ISA has an overwhelming market share in mobile device chips and continues to expand into a variety of embedded applications. Arm provides licenses in soft and hard core licenses, and soft cores can acquire instruction set architectures. The hard core can only obtain the wafer circuit that has been realized by a certain semiconductor process technology.
Arm tends to provide hard core licenses to avoid core technology leakage, but some heavyweights have access to soft core licenses, such as Qualcomm, and it is generally speculated that Apple, Samsung, etc. are also listed. GreenWave said that he wants to get a soft core license of at least $15 million, and only for time use.
Since the technology ecology of the ISA is becoming more and more complete once a lot of chips or software are adopted, the owner of the ISA architecture will be regarded as easy to enjoy profits in the future. Chip vendors (chip vendors without ISA autonomy) System vendors and end users will all suffer. To this end, in 2010, the academic and industry community jointly initiated the establishment of the RISC-V Foundation, and continued to promote ISA with open technical details and free technical licenses.
Open and free licensing, from the perspective of another key component operating system in the information technology industry, the early operating system was developed by computer system vendors along with their own hardware, and shipped with hardware sales, such as IBM After the host. IBM eager to cut into the PC market, adopt Microsoft's operating system, and then open the software-only commercial license mode of the operating system across different systems vendors, but the operating system code is still owned by Microsoft, and then Linux rises. , the code is open and free to use.
This development process corresponds to ISA, Intel's ISA is shipped with its own chip, Arm is licensed across the chip vendor's ISA, but they are all proprietary and charged, and RISC-V tries to emulate Linux, open and free Way to develop.
RISC-V adopts BSD license
Although RISC-V adopts an open free route, it is different from other open-source silicon intellectual property projects, for example, it has its own hardware description language (HDL), which is Chisel (Constructing Hardware In a Scala Embedded Language). From the full writing, you can understand that it is based on the Scala language. Chisel also adopts the open source policy. Compared to the commonly used hardware description language, Verilog is widely used, but there are tools to convert the circuit developed by Chisel into Verilog format, then modify its design, or integrate with other circuits.
RISC-V is licensed under the BSD license, rather than the GPL license common to open source software. If the GPL is authorized, the extension development must also be licensed by the GPL. The original code must be opened (the mainland is called the original code, Source code), but many operators want to maintain a competitive advantage, and treat their own developed programs as trade secrets rather than open. In fact, Android is also rewriting the Linux kernel, so that hardware vendors adopting Android operating systems do not need to be open. Its driver, retaining its confidentiality, has won numerous mobile phone support for Android.
But BSD is different, BSD allows the use of its open results, but the extended software does not need to be open, obviously more generous than the GPL. As for the compiler, related software support, there are already gcc/glibc/GDB, LLVM/Clang, Linux, Yocto, Verification Suite and other software.
RISC-V is a good idea, but if the actual chip is not performing well, it is still difficult to compete with the commercial ISA. The RISC-V's leading academic unit, UC Berkeley, has developed a RISC-V. The Rocket RISC-V chip was deliberately chosen to compare with the Arm core (Cortex-A5) implemented by the same process (TSMC 28nm) technology (Figure 2).
First, compare the clock frequency, both of which can reach 1GHz or above, which is considered as a tie; in terms of performance, the RISC-V Rocket can reach 1.72DMIPS/MHz, which is about 10% higher than the Arm Cortex-A5; In the wafer area occupied by the core, the RISC-V Rocket is only 0.14 square millimeters, only half of the Cortex-A5. Even if both of them contain 16KB of cache memory, only 70% of the A5 is used. Every square millimeter, the performance of Rocket can reach 1.5 times that of A5. In terms of power consumption, Rocket is about 40% of A5.
However, this comparison still has a little foothold. Rocket adopts a 64-bit architecture, but RISC-V also has a 32-bit architecture. If both are 32-bit or 64-bit versions are used. , perhaps more fair comparison. In addition to Rocket, there are 8,9 implementation cores such as ORCA, PULPino, etc. The aforementioned GAP8 is based on PULPino.
In addition to the MCU/CPU core technology, RISC-V also actively develops the core interface technology required for the core, namely TileLink. The reason is that Arm also lays out the interface technologies and protocols required between cores and cores and peripherals in addition to core technologies. Therefore, there are AMBA agreements, ASB bus bars, APB bus bars, etc., and subsequently extended to develop AHB, ATB, AXI, ACE, CHI and other interfaces.
RISC-V is not the first open project
Although RISC-V is an open hardware project that has recently received increasing attention, it is not the only or the earliest project. It has been OpenRISC, OpenSPARC, etc., but such projects have encountered some development restrictions after launching. The OpenRISC architecture is old and slow to develop. The 64-bit version of the architecture is not mature enough. OpenSPARC comes from the UltraSAPRC, which gradually loses its price-performance ratio. The open community is not active (Figure 3).
In addition, some projects are too academic and theoretically functional, but when implemented as actual circuits, it is not easy to improve performance, reduce power consumption, reduce wafer area, etc., or some projects are not easy to import software assets already available in other ISAs. (drivers, sample programs, applications, etc.), it is difficult to recompile and rewrite.
All of the above, RISC-V has been considered at the beginning of its establishment. The new architecture planning definition from scratch must be close to commercial implementation, and it is also convenient to guide the software assets of other existing ISAs. Therefore, many semiconductor industries have been established since its inception. Big companies participate together and ensure that the community develops energy.
It is worth mentioning that the chip makers of the proprietary architecture have changed their attitudes in recent years, no longer only sell complete chips, but also emulate Arm's business model, allowing the core technology of the chip to be re-developed, such as Intel's cooperation with TSMC in 2008. Open x86 core license, allowing other players to develop their own chips with x86 architecture, or NVIDIA will open its GPU core licenses in 2013, but such licenses, its ISA patents and subsequent development trends are still dominated by chip vendors, not Participation in the formulation, this derivative business has not been carried out so far.
IoT/AI is suitable for RISC-V
An ISA technology ecosystem can be successful, and must have advantages in terms of technical characteristics and scale. For example, the x86 ISA has the best price performance ratio and is widely used from the PC, while the Arm is low-power, per-watt performance ratio. Therefore, it is widely used on mobile devices such as mobile phones and embedded devices. Therefore, RISC-V also maximizes the applicability of ISA. Therefore, 32-bit, 64-bit architecture is also developed, and the addressing method is widely supported. 16/32/64/128 bit addressing.
In actual development, it is true that all types of applications are in development. The aforementioned GreenWave developed GAP8 chip is to lock IoT applications, using TSMC 55LP (Low-Power) process, the target market is similar to Arm Cortex-M0~M7. WD invested Esperanto Tech, which uses RISC-V to develop artificial intelligence (AI) chips, with a 64-bit architecture, and develops 16 core ET-Maxions and 4,096 core ET-Minions. Use TSMC 7 nanometer process.
In addition, FPGA chip maker MicroSemi also proposed RV32IM's RISC-V soft core technology, which enables chip developers to use FPGA chip evaluation and analog design in the early stage. If they want to cast a commercial mass production chip in the future, the cost of core authorization can be avoided. In the past, if Arm core development, there are licensing fees, premiums and other concerns.
In addition, some companies have tried to use the RISC-V architecture but adopt the same silicon intellectual property licensing model as Arm. For example, SiFive and Andes, SiFive introduced 32-bit (RV32) E31 core and 64-bit (RV64) E51 core. The 28nm process is used. The former locks the Cortex-M3 and M4 applications, and the latter is similar to the Cortex-A53. However, E31 and E51 do not support Linux. However, Linux is widely used in the embedded field. For this reason, SiFive Also proposed is the U54/U54-MC (RV64GC) core, which supports Linux (Figure 4).
Andes also proposed the AndeStar v5 architecture (ie root based on RISC-V), including 32-bit N25 core and 64-bit NX25 core, also adopting 28nm HPC process, and stressed that only a few logic gates are needed. It can be realized that N25 only needs 30,000 logic gates, and NX25 is 50,000. The less the logic gate is used, the less wafer area is needed, which means that the chip can be realized and produced at a lower cost. CEVA also has only The 32-bit RISC-V (RV32IMC) is implemented using 20,000 less than the logic gates, and is set for use in Bluetooth, Wi-Fi transceiver chips.
In addition, although it is based on RISC-V, Andes still makes various enhancements to it, such as using custom instructions to reduce the code size by 10%, which can reduce the program memory requirements; or accelerate the instant processing when interrupts occur. Speed, more suitable for immediate applications; or protection of the stack to prevent malfunction or reduce security issues.
RISC-V member lineup is strong
There have been many reports about the RISC-V in the big factory. It has only been taken quickly. For example, NVIDIA's GeForce graphics processing unit (GPU) has a Fast Logic CONtroller (Falcon) controller, and the new Falcon will adopt RISC. -V architecture, Samsung will also be used in its own mobile chip, WD will also be used in a variety of chips. The above reason why the industry has embraced RISC-V for no reason, these companies are heavily used or sold chips, the past adopted Arm The core has to pay a huge technical fee, and if it is changed to RISC-V, it will save a lot of money.
On the government side, there are DARPA-funded commercial companies in the United States to develop aerospace equipment chips based on the RISC-V architecture. The Indian government also strongly embraces RISC-V; academic institutions have 35 universities, including many famous universities, such as the Massachusetts Institute of Technology. Princeton University, etc. (Figure 5).
Business model turns into the biggest worry
RISC-V seems to have developed smoothly so far, but in fact, there are a number of hidden concerns. First, RISC-V allows the adopters to extend the definition instructions themselves. If each line will split the software compatibility, it will be in a backward position. Software ecosystem is more difficult to cohesion development.
The other is the transformation of the business model of new entrepreneurs. Taking the aforementioned SiFive as an example, the original expected business model is based on the free RISC-V architecture, accepting the customer's customized commission design, and charging the design fee, but then turning into The core of the developed core is charged $300,000 for the E31 and $600,000 for the E51 (the 64-bit version of Andes claims less than $1 million).
SiFive's license is still more generous than Arm, 300,000, 600,000 US dollars for a one-time fee, Arm is in addition to a one-time fee also for each chip to receive royalties, and RISC-V still has modifications, free flexibility However, SiFive turned to the same route as Arm, and it also worried whether it had violated the original intention of RISC-V.
In addition, in the past, the development of open source software, in addition to encountering the inconvenience of community inactivity, the controversy of subsequent development routes, or parting ways to develop, or still focus on development, but the route gradually deviated from the original intention or commercial value, etc. These can also happen on the RISC-V project.
Finally, Taiwanese companies are also highly interested in RISC-V as a new development opportunity, such as TSMC can get more investment orders from new chip makers; Andes does not stick to its own core architecture and embrace RISC-V Even if the architecture is incompatible, it will not give up the new machine; MediaTek (MTK) also joins the RSIC-V Foundation; chip design service provider Faraday is also looking forward to the new development.