The market favors low-cost high-performance products, and packaging solutions continue to face challenges and innovations. Fan-out packaging technology began in 2006, and after ten years of precipitation, it has experienced explosive growth in 2016. Currently, fan-out packages are mainly concentrated. At the wafer level; however, the limited utilization of wafers and their high cost hinder their high volume manufacturing. High performance from wafer level to panel level, low cost packaging requirements, driving the semiconductor industry to develop innovative solutions Transforming wafer-level packaging into large-scale board-level packaging is a new way to reduce overall costs. With mature technology, costs can be reduced by 50% and product yields exceed 90%. In fact, board-level process infrastructure Has aroused great interest in the semiconductor industry, with cost advantages and economies of scale, is a promising market. Various factors are driving the development of board-level fanout packaging (FOPLP) and encouraging the entire industry chain (including equipment) And materials) Investing in board-level fanout infrastructure has become an important strategic layout on major OSAT roadmaps. Current players include ASE, SEMeCO, NEPES, Intel, SAMSUNG.
Market application and challenge of large panel fan-out package The fan-out package market is currently focused on single-chip package applications such as baseband, power management and RF transceivers, as well as mobile application processor chips, dynamic memory chips, automotive radar and driverless high-density multi-chip stacked package applications. Out-of-package technology is moving toward next-generation packaging such as multi-chip, thin package and 3D SiP, not only for electronic packaging, but also for sensors, power ICs and LED packages. Achieve small size, higher integration and functionality, its applications include drones, automotive side collision avoidance systems, automatic parking devices, etc.
After years of process and technology development and verification, FOPLP has finally entered mass production. According to Yole Développement, the overall fan-out packaging market is expected to grow from $244 million in 2015 to $2.3 billion in 2022, FOPLP market revenue It is expected to reach approximately $280 million by 2023. Powertech Technologies (PTI), NEPES and SEMCO are expected to enter FOPLP mass production by the end of 2018. NEPES is primarily aimed at (L/S>10um) automotive, sensors and IoT-related Application, PTI and SEMCO's long-term goal is L/S <8/8或更小线宽线距的中高端应用. 其余各大OSAT, 如ASE, Amkor, JCET/STATS CHIPPAC等, 也在评估技术方案, 每个玩家都在基于自己的战略路线和设备设施进行板级扇出封装技术的研发和布局.
Opportunities and challenges coexist. There are still many challenges in the development and industrialization of FOPLP. The industry standards are missing. Due to the different application fields and customers, the process and panel sizes used are not the same. It is difficult for end users to choose according to uniform standards. Equipment manufacturers are also unable to design equipment that meets different size requirements, and the production line facilities are expensive. In addition, there are a series of technical difficulties that need to be overcome, such as warpage control, patch accuracy, and manufacturing RDL less than 10/10um on large panels. Lines, etc. FOPLP must be standardized for industrialization, such as board size and assembly process standardization. According to Yole Développement's market research report, most players currently support a relatively simple design: L/S>10/10 um, package size <10 x10 mm2, 最多2层RDL. 随着技术和经验的成熟, 最终将采用高密度设计: L/S <10/10 um, 多层RDL, 封装尺寸> 15×15 mm2 and multi-chip SIP integration.
Huajin's accumulation and development in FOPLP In 2015, Huajin joined 25 domestic and foreign companies to establish a large-panel fan-out complex, focusing on the development of 320mm×320mm board-level fan-out technology, forming a complete system including end users, design, package foundry and materials. Industry chain. Our consortium members include Huawei, Tongfu Microelectronics, Shennan Circuit, Silicon Precision, JSR, SCREEN, DeLong Laser, Lianzhi Technology, ASM, SCHOTT, ATOTEC, ORC, SEKISUI, Sumitomo, Shanghai Wei Electronics, Technology, etc. During the operation of the consortium, completed the single-chip and single-layer RDL design work, and completed the simulation and simulation work of heat, mechanical and warpage; integrated the industrial chain of the board-level fan-out, Developed Die First (Die-in) and Die Last (substrate-based) process routes to complete sample flow and reliability verification; formed the core intellectual property of large-panel fan-out, applied for 5 large-plate fan-out cores Patented; evaluated and validated equipment and materials for FOPLP consortium members, such as SCREEN's SLIT coating coater and laser direct writing exposure machine, ORC's PPS lithography machine, ASM's placement machine, TOWA's laminator, AOTOTECH plating machine, KINGYOUP Sublayer PVD sputtering machine, SUMITOMO powder molding material, NAGASE liquid molding compound, JSR photoresist/PI/temporary bonding material, etc. The project results won the '12th (2017) China Semiconductor Innovation Products and Technical project' .
Huajin's first slab fanout consortium member
Huajin's first large-scale fan-out sample
With the close of the first phase of the consortium, in response to the strong demand of the majority of members, Huajin has begun preparations for the second phase of the consortium. According to feedback from a number of equipment/material suppliers at home and abroad, combined with the draft of SEMI drafted by Huajin A standard FOPLP board size standard, the second stage board size is set to 600mm x 600mm, the main development of multi-chip and multi-layer board-level fan-out package technology development, training a professional FO R & D team, provide design from Simulation, process to reliability analysis and testing of the FOPLP overall solution, the final goal to establish a process demonstration line. The specific process parameters are as follows:
In view of the successful operation of the first phase, a number of new members will be introduced in the second phase. The project start-up will be held in early September. At present, there are more than 20 intentional member units, and the scale is expected to be much higher than the first phase. The members of the consortium will participate in the FOPLP process technology. Develop, share the resources of the consortium platform, verify and develop equipment and materials, and propose optimization solutions. Give priority to the patents formed during the project period, and enjoy the admission and sponsorship of Huajin Open Day and Huajin & Yole seminars. priority.
