Three-dimensional integrated circuits are the key to maintaining the rapid development of the integrated circuit industry, and three-dimensional memory is the leader in three-dimensional integration technology. Three-dimensional new non-volatile memory is being transformed into an existing computing architecture due to its unique speed, density and longevity advantages. The high hope is the focus of international competition. As one of the two mainstream array structures of the new three-dimensional non-volatile memory, the current research on three-dimensional vertical array structure mainly focuses on the device and array level. However, the three-dimensional memory is in the vertical direction. Integration, new biasing methods, and new memory devices have impacted the speed and reliability of the chip, presenting significant challenges to the chip design methodology of 3D memory.
In response to this challenge, Lei Yu et al., Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences, first proposed a new bias method for three-dimensional vertical memory. Compared with the traditional bias method, the new bias method supports single bit reading in the sub-array. , reduced power consumption, improved read/write speed, improved read accuracy; designed chip array core circuit according to new bias method; analyzed main factors affecting chip readout operation; proposed change reference and parasitic matching readout circuit The circuit has fast reading speed and high reading accuracy, and can be applied to various types and sizes of three-dimensional vertical type memories; experimental results show that: the proposed readout circuit has a random reading time of 75% shorter than the conventional method. The number of misreads for typical and worst resistances is reduced by 100% and 95.31%, respectively, compared to conventional methods.
This paper summarizes and analyzes the main factors affecting the readout operation of three-dimensional vertical memory for the first time in the world, and proposes the first integrated circuit design of three-dimensional vertical type new memory. It is also the world's first three-dimensional vertical type new memory integrated circuit design. The research results provide a technical reference for the engineering implementation of 3D vertical memory and promote the advancement of 3D memory chip design methodology.
Lei Yu is the first author of the thesis. The research work was carried out under the leadership of researcher Song Zhiwei. The research work was supported by the Chinese Academy of Sciences' strategic pilot science and technology project, the National Integrated Circuit Major Project, the National Natural Science Foundation, and the Shanghai Science and Technology Commission.