China's first policy to support RISC-V
According to the requirements of the Notice, the application must meet four conditions, including: (1) The reporting unit must be a unit established in accordance with the law and capable of independently undertaking civil liability. The operating status is normal, the credit record is good, and it conforms to the industrial development orientation. Have the corresponding ability to undertake project construction; (2) The content of the declared project must be within the scope of the project guide; (3) The reporting unit must seek truth from facts and report the relevant economic, technical indicators and fund implementation that need to be realized scientifically and reasonably; The implementation period of each project is within two years (2018.7.1-2020.6.30).
Project Guide to Processor Chip Direction Based on RISC-V Instruction Set Architecture, Annex to the Notice "The Second Batch of Shanghai Software and Integrated Circuit Industry Development Special Funds in 2018 (Integrated Circuits and Electronic Information Manufacturing Sector) Project The Guide states:
Support R&D and industrialization of 32-bit and above processor chips based on RISC-V instruction set architecture. The kernel needs to have independent intellectual property rights.
Direction 1: For the Internet of Things and industrial control applications, with excellent performance, power consumption, area and other indicators, priority to support projects with clear user cooperation agreements. The cumulative sales revenue during the project execution period is not less than 20 million yuan.
Direction 2: For intelligent terminal applications, the main frequency is no less than 1GHz, the performance is not less than 1.5 DMIPS/MHz, support double-precision floating-point operation, support mainstream operating system, multi-core technology and cache consistency. Accumulated sales during project execution period The income is not less than 10 million yuan.
Arm pressure
As an important city for the development of the domestic integrated circuit industry, the Shanghai government has been actively supporting the development of integrated circuits. This may be the key to Shanghai's first policy to support the development of RISC-V. RISC-V is also a streamlined instruction set, with current mobile devices. Compared to the Arm instruction set used in the RISC-V instruction set, it can be used freely for any purpose, allowing anyone to design, manufacture and sell RISC-V chips and software.
Although not the first open source instruction set, RISC-V's recent development seems to put pressure on Arm. At the end of June, Arm established riscv-basics.com's website to 'five things to consider before designing a system chip' Themes attacked RISC-V attacks in terms of cost, ecosystem, fragmentation risk, security and design assurance. However, RISC-V also established arm-basics.com's website on July 9 to counter Arm. On July 10th, Arm closed the attack site and issued a statement: 'Our original website was created to list the key factors that need to be considered around RISC-V commercialization products, designed to provide a fierce industry debate. Information. Unfortunately, the results are different from our original intentions. This page is inconsistent with Arm's collaborative culture, so we have removed it. In fact, many of our employees also expressed dislike of this page. Arm and RISC-V events Just a microcosm of the competition between two streamlined instruction sets, OURS founder and CEO Tan Zhangyi said: 'IoT application will be accompanied by new technology, RISC-V is very likely to replace Arm, of course, Arm will not disappear, but in IoT city
A good era of the RISC-V instruction set
Of course, the recognition of RISC-V is closely related to the measured data of its prototype chip. In 2011, the Berkeley research team designed and implemented a 64-bit processor core (codenamed Rocket) based on the sequential execution of the RISC-V instruction set, based on 45nm and The 28nm process has been performed 12 times. The Rocket chip has a main frequency greater than 1GHz. Compared with the Arm Cortex-A5, the measured performance is 10% higher, the area efficiency is 49% higher, and the dynamic power per unit frequency is only 43%. These data indicate RISC. The -V Rocket processor core is already very competitive. Subsequently, the Berkeley research team introduced the open source SOOM (Berkeley Out-of-Order Machine), enabling the performance of RISC-V to reach Arm. High-end processor level. In 2015, the Berkeley research team established the startup SiFive to accelerate the commercialization of RISC-V.
Also in 2015, the non-profit organization RISC-V Foundation (RISC-V Foundation) was established, attracting hundreds of units in two years, including Google, Huawei, IBM, Micron, NVIDIA, Qualcomm, Samsung, Western Digital, etc. International leading companies and academic institutions such as UC Berkeley, MIT, Princeton University, ETH Zurich, Indian Institute of Technology, Lorenz National Laboratory, Singapore Nanyang Technological University and Institute of Computing Technology of the Chinese Academy of Sciences. Enterprises and research institutions through RISC- The V Foundation can participate in the evolution of the instruction set specification and the development of the software and hardware ecosystem.
Member of the RISC-V Foundation
RISC-V has become the Indian National Command. In 2011, India implemented the Processor Strategic Plan to fund 2-3 projects for the development of processors nationwide. Two professors at the Indian Institute of Technology, Madras, supported the program. The SHAKTI processor project was launched and the IBM PowerPC-compatible processor was developed. In order to obtain legal authorization, the SHAKTI project team negotiated with IBM, but failed to reach an agreement. At this time, it happened to encounter RISC-V in 2013. The film was successful, so the SHAKTI project team gave up PowerPC to embrace RISC-V, and the project goal was temporarily adjusted to develop six open source processor cores based on the RISC-V instruction set. This temporary adjustment was not only blamed, but rather the Indian government. In addition, in January 2016, the Advanced Computing Development Center, which has been conducting supercomputer research for a long time, received a grant of US$45 million from the Ministry of Electronics and Information Technology of India. The goal is to develop a 2GHz quad core based on the RISC-V instruction set. Processor. Also, in another project on neuromorphic accelerators supported by the Indian government, RISC-V is also used as the main core of computing. With the support of the Indian government
In addition to the Indian government, the US DARPA, the Israel National Innovation Agency also chose to develop a processing platform for national enterprises based on RISC-V. Today, the Shanghai government is also the first to support the RISC-V architecture chip, which represents RISC-V in China. A good time has arrived?