Cadence launches Voltus-XP | Supports large-scale advanced process node power sign-off technology

楷登电子 today announced the release of the enhanced Cadence® Voltus IC power integrity solution for grid sign-offs for advanced process nodes, and its massively parallel (XP) algorithm option uses distributed processing technology. Up to 5x for gigabit designs. The massive parallel processing of the Voltus solution has been greatly enhanced to more efficiently achieve near-line performance expansion of thousands of CPUs on hundreds of devices. The solution is now cloud-ready.

In mobile applications, high-performance computing (HPC), machine learning, artificial intelligence, networking, automotive and other advanced process applications, Voltus-XP technology is undoubtedly the ideal choice for ultra-large chip design power signing. New massively parallel algorithm Provides greater capacity, combined with Cadence SigrityTM technology, not only grid IR drop and electromigration (EM) analysis, but also 3DIC chip-package board system-level electrical and thermal synergy analysis, full-chip SoC design flow can be more Smooth.