Episode News (Text / Xiaobei) Recently, eSilicon introduced the NeuASIC ASIC design platform manufactured by TSMC's 7nm process, including hardware and software macro commands for network applications and new architectures and IP libraries for building AI accelerators.
The NeuASIC platform provides designers with a variety of power-optimized memory compilers, SerDes and 2.5D IC packages. The 7nm library includes 56Gbps SerDes, HBM2 PHY, Tri-State Content Addressable Memory (TCAM) compiler, network-optimized I/O and Other components.
In 2017, Marvell closed most of its European operations, and eSilicon thus “acquired” Marvell's team of Italian engineers who developed a 56 Gbps SerDes for 28-nm process for Marvell. The team developed with the same architecture based on ADC/DSP. The 7nm 56Gbps SerDes is out, and the core appears on the NeuASIC platform. At the same time, the core can be licensed separately. For the chip, power consumption and performance seem to be two indicators that cannot be considered at the same time. The SerDes core PAM4 and NRZ encoding can be implemented, and its programmability allows designers to perform long/short channel performance and power consumption adjustments.
SerDes is short for Serializer/Deserializer. As the name implies, it is a serializer and a deserializer. However, SerDes is only described as a serializer and a deserializer. This explanation is not complete. In addition to the serializer and deserializer, the SerDes system also Including the driver side of the transmitter and the analog front end of the receiver. For the low-speed SerDes system, the design of the analog front end is less difficult and the power consumption is low. The use of the ADC will increase the design difficulty of the system. For the high-speed SerDes system, the implementation is high. The high speed ADC of accuracy is inherently more expensive than implementing an analog front end.
In April, MediaTek launched the industry's first 7nm 56G PAM4 SerDes IP. The solution is based on DSP technology and uses high-speed transmission signal PAM4, which is expected to be available in the second half of 2018.
Both eSilicon and MediaTek's SerDes solutions can achieve 56Gbps and adopt a 7nm process, which may form a competitive relationship in the future.
SerDes is part of the NeuASIC platform, and 'communication' is one of its important tasks. The implementation of NeuASIC AI performance is mainly in its AI accelerator, etc. The integration of AI accelerators is relatively 'new', and this has a large package with NeuASIC. relationship.
In order to maximize the bandwidth of the memory, the eSilicon NeuASIC network communication chip stacks the ASIC and DRAM through a silicon interposer and encapsulates it with 2.5D package technology. For AI accelerators, NeuASIC allows designers to implement Deep Learning Accelerator (DLA). Converged into the ASIC, as shown below. The industry believes that this is a brand new way.
