Ryan Sanghyun Lee, Vice President of Samsung Electronics Foundry Marketing Team, said: 'By intensive cooperation with Synopsys, our 7LPP process certification and reference process will achieve the lowest power consumption and best performance for our common customers. And the optimal area. Using the Synopsys Design Platform, which has been proven and integrated with Fusion technology, our foundry customers can confidently use Synopsys' most advanced EUV process to mass produce their designs.
Michael Jackson, vice president of marketing and business development at Synopsys' Design Division, said: 'Our collaboration with Samsung's tools and reference processes is focused on enabling designers to use Samsung's latest EUV 7LPP process to achieve the best results with the highest level of confidence. Using the Synopsys Design Platform with integrated Fusion technology, the scalable 7LPP reference flow will enable designers to easily achieve their desired design and time goals.
The 64-bit Arm Cortex-A53 processor based on the ARMv8 architecture is used for quality of results (QoR) optimization and process certification. Key tools and features of the Synopsys Design Platform 7LPP reference process include:
IC Compiler II Layout and Routing: EUV single exposure based wiring with optimized 7LPP design rule support, and row puncturing to ensure maximum design splicability and utilization while minimizing voltage drop.
Design Compiler Graphical RTL Synthesis: Correlation with place and route results, reduced congestion, optimized 7LPP design rule support, and physical guidance to IC Compiler II.
IC Validator physical signoff: High performance DRC signoff, LVS perceptual short finder, signoff padding, pattern matching and unique Dirty Data analysis with Explorer technology, and in-design verification with DRC auto-repair and in IC Compiler II Accurately sense the timing of metal filling.
PrimeTime timing signoff: Near-threshold ultra-low voltage variation modeling, via change modeling and engineering change order (ECO) guidance for perceptual layout rules.
StarRCTM parasitic extraction: EUV is based on single exposure mode routing support, as well as new extraction techniques such as coverage based via resistance.
RedHawkTM Analysis Fusion: ANSYS® RedHawkTM driven EM/IR analysis and optimization in IC Compiler II, including via insertion and grid amplification.
DFTMAXTM and TetraMAX® II testing: Based on FinFET, cell sensing and timing margin based conversion testing for higher test quality.
Formality® Form Validation: Based on UPF, equivalence check with state transition verification.
The scalable and referenced process that is compatible and certified with Synopsys Lynx Design System is now available through the SAFETM program. The Lynx Design System is a full-chip design environment with innovative automation and reporting capabilities to help designers implement and monitor their Design. It includes a production RTL-to-GDSII process that simplifies and automates many key design implementation and verification tasks, enabling engineers to focus on achieving performance and design goals. SAFETM plans are supported by Samsung Certified and extensively tested Process Design Kit (PDK) and reference flow (and design methodology).