Hardware design that is not for the purpose of filming is a rogue?
In this DAC's keynote, we also saw the arrival of the four Turing Awards, David Patterson, and he also wrote (Pinyin: ruo4) 叕 (Pinyin: zhuo2) to talk about this unchanging topic, ( A year ago, Silicon said that it was a topic of talk: RISC-V and DSA! Computer Architecture Guru Patterson and Hennessy speech record)
However, as a responsible amnesty, Patterson is still a lot more new than the ISSCC talk (video URL: https://youtu.be/NZS2TtWcutc, remember to over the wall), such as the security perspective after the Spectre incident. Reflection on the architecture. However, Xiaobian feels that the other two points are extra prominent:
(1) Today, Moore's Law is advancing rapidly. The rapid reduction and saturation of integrated circuit manufacturing costs have almost disappeared from the entry barrier of chip design. Now, the unit price of 1x1 square millimeter 65nm design has dropped back to 5K US dollars, even 28nm. 20,000 knives. The following picture is the quotation of esilicon 2016 for each node of TSMC (2mm x 2mm, 28nm is 1.6mm x 1.6mm, unit of euro, can be Google)
This has already reached the one-month salary (after tax) of the North American Silicon Workers and Farmers. It will be able to flow with RISCV and NVDLA. Is it expensive?
(Where is there a proxy for streaming 1x1? There are MOSIS and Muse in North America, and there is a 'Moore Star' university program in Tianchao, so there is no hard-to-do chip buying plan for colleges and universities.)
The fact is that the cost of streaming is getting higher and higher, and the cost of EDA software/design verification/back-end implementation has risen exponentially compared to the steady development of manufacturing costs. The industry calls this type of cost NRE (non recurrent engineering) , one-time project costs).
What's more, SiFive's chief architect, UCB professor, RISCV Foundation Chairman Krste Asanovic believes that the Moore theorem should be corrected, not the manufacturing cost of the unit transistor is reduced, but the NRE drop for the implementation of a transistor. 2018, session 59)
(2) With the essence of Moore's law stopped (unless you are Apple Huawei, you can basically worship below 10nm. The actual situation is that many colleges have actually stopped at the 40/65 node), plus the power limit of dark silicon. Domain Specific (DS) design is an irreversible trend. After all, dedicated design can easily increase efficiency by 2 to 3 orders of magnitude.
In this DAC speech, Domain Specific is not limited to DS Architecture, but also emphasizes the burst of DS language, and quickly, in DSA and DSL, through hardware / Sofware codesign A new era of IT -
CS (software) and EE (hardware) are one.
It sounds like this spring and autumn dream is still very far, but 10 years in this century will not be too long.
Under these two trends, whoever holds the agile development methodology with low NRE costs will become the new overlord in the post-Moore's Law era.
People’s government, paying more attention
Perhaps the earliest awareness of this urgency is the Defense Advanced Research Projects Agency (DARPA, part of the US Imperial Defense Department). In 2015, DARPA established an integrated circuit project for agile development methodology. Realization At Faster Timescales (CRAFT). Among them, the object-oriented design methodology is particularly emphasized. Does it feel that hardware design is experiencing the era of software engineering from C to C++?
In the traditional ASIC era, the traditional idea of algorithm description, hardware description, RTL to circuit netlist to layout (there is feedback verification at each stage) will be broken and become an object-oriented feedforward methodology. Designing to the layout may take only a few days, or even hours.
One of the most representative products of the CRAFT project is CHISEL (and CHISEL2/FIRRTL), a new star in the RISC-V era.
Chisel is a concept to implementation, which perfectly reflects the original intention of agile development. It is worth noting that CHISEL is separated from the essence and HLS. It can be seen that Chisel leads the wave of agile hardware development.
In addition to colleges and universities, major companies are actively following up on the CRAFT project. For example, NVDIA's new generation of small-scale AI embedded chips in DAC 2018 present, the design process uses object-oriented HLS to realize the design and verification of the entire chip. The collection of SystemC and Chisel shortens the traditional design development cycle of the past three years to three months.
In 2017, the CRAFT project is in the ascendant. DARPA has increased the code and proposed the Electronic Resurgence Initiative (ERI). The third page of this paper, which focuses on Moore's Law, proposes billion levels in the three directions of design/architecture/material. In the design direction, DARPA puts forward the ultimate goal of ERI: to go to the chip design experience like Amazon/Jingdong/Taobao shopping, top up the shopping cart, and a make (single order) chip is sent home.
Based on CRAFT, ERI's design section emphasizes No-human-in-the-loop and open source systems. Redefining the way circuits are generated, especially custom circuits (analog and mixed-signal, etc.), abandoning traditional labor-intensive Development model, which is moving towards a comprehensive model driven by data and intelligence:
In this process, open source design is one of the most important aspects, because only enough open source can promote the efficiency of the labor force. In today's Internet, the battlefield must be able to occupy a place on the chip battlefield. Silicon said that open source has become a new trend in chip design. DARPA plan, at the end of the ERI project, the following total IP can find the open source version:
From this point of view, the layout of human research institutions in this field can not be said to be ahead of the game, and the next is a full game of chess. And we are still wandering in the bubble of artificial intelligence.
Analog / RF / mixed signal, one can not quite
Traditionally, our open source, and agile design are all digital-oriented. The design methodology of analog (traditional custom circuits) circuits has not changed dramatically. However, this view seems to also receive challenges.
UC Berkeley BWRC team, while designing CHISEL, also designed the analog version of CHISEL - Berkely Analog Generator (BAG), also released BAG2 when CHISEL2 was released. In the 2018 CICC, BAG2 announced their research The result - the analog circuit generator across the process. In the redefinition of the different modules of the expression layer (Intermediate Representation, IR, the word is a compilation term, but now used in the analog circuit design) after the different process pdk , automatically generate netlists and layouts, not only DRC/LVS error free, performance is not bad. In the world of BAG2, as long as you will python, you can design GDS. For details, please refer to DAC 2018 session 41.2, and CICC 2018 15.2.
On this DAC, similar analog/RF circuit generators are overwhelming, including AIDAsoftware Software Inc. from Portugal (in cooperation with the University of Macau).
Imagine that in the future, Tianchao's chip design company is still working overtime, in order to survive the performance of a corner, the layout of the small workers are all night long. The layout of the Pacific Ocean, It is free optimization in the server, no human in the loop.
Perhaps the EDA design for generators has been proposed for many years, then ignored, and then raised, and then ignored. However, today, when Moore's Law ends, in the field dedicated to the future, the market is constantly being subdivided. Today, the official agile design SoC real spring.