The efficiency of the memory array is about 57% due to relatively large memory and other peripherals; while the efficiency of the SK Hynix 36L and 48L product memory arrays is 67.5% and 64.0%, respectively. This trend shows that SK Hynix should be the next generation The chip develops a more compact design.
The 64L 3D TLC NANS die from Samsung and Toshiba/WD (Toshiba/Western Digital) has more than 65% memory array efficiency; however, the above memory chip sizes and functions are similar.
The bit density of SK Hynix 72L NAND flash memory is 3.55 Gbits/mm2, which is higher than the 64L chip of Samsung/WD; and the 64L 3D NAND chip of Micron/Intel is the highest bit density among 4 solutions. The main reason is the use of a unique brick layout called CuA (CMOS under the array).
In the 3D NAND memory cell architecture, the SK Hynix chip stacks a total of 82 gates, including selectors and dummy wordlines (DWLs); we know that 72 gates are used for active characters. Line unit, and the top three gates are the selector gates (SG) for the source and the drain. The remaining 7 gates should be used for DWL and isolation gates. ).
In the 64L NAND components of various manufacturers we see:
Samsung uses a total of 71 gates, of which 3 are for SG and 4 for DWL; the total number of gates for Toshiba/WD products is 73, of which 7 are for SG and 2 for DWL; Micron/ The total number of gates for Intel products is 76, of which 2 are for SG and 7 for DWL.
The vertical cell efficiency calculation method is the number of active word lines divided by the total number of vertical stack gates; the result is the process efficiency of the 3D NAND memory cell architecture. The vertical cell efficiency of SK Hynix 72L products is 87.8%, Toshiba/WD The same is true for 64L BiCS products; Samsung's 64L product efficiency is 90.1%, while Micron/Intel's 64L product efficiency is 84.2%, as shown below.
Vertical Unit Efficiency of 64L and 72L 3D NAND Memory Products (Source: TechInsights)
SK Hynix's previous 36L and 48L products use a single-step etching process to create channel holes for 43 and 55 gates, respectively; a new generation of 72L memory cells is produced using a two-step etching process. Lead to the hole. At the gate of the pipeline, the lower 42 gates and the upper 40 gates are formed in two different etching steps. The slits and subslits (subs) -slits) are formed in a single step of etching. The process integration procedure is as follows:
Pipeline gate molding (lower part) Channel etching (lower part) Sacrificial layer filled in holes; Molding (upper part); Channel etching (upper part); Sacrificial layer removal;
Micron/Intel's 64L products use a dual-stack NAND string architecture with a plate between the upper and lower stacks, while SK Hynix's 72L products use a two-step etch process rather than a dual stack NAND string. Engineers must strictly control the process steps to avoid misalignment of channel holes in the upper and lower parts; the size of the holes is only about 10 nm in the 256 Gbit 72L product. For more information about the analysis of SK Hynix 72L NAND flash memory, please click here Link reading.
Compilation: Judith Cheng