AI chip three paths will have variables?

Currently, there are mainly three kinds of AI chips on the market. One is to execute AI algorithms with traditional chips, such as CPU, DSP, FPGA, etc. The second is GPU + AI accelerator, which implements AI functions. The third type is customized. ASIC. These types of paths have their own advantages, but they are also flawed.

Like a huge 'magnetic field', AI's gravitation has gradually moved from a technological revolution to industrial development. As the core of AI technology, AI chips are also attracting attention, not only to meet the needs of AI computing, but also to adapt to different requirements. Application scenarios and different locations (cloud or end). The battle for AI chips also presents a variety of genres, each with its own fans, who will win?

Three paths

Currently, there are mainly three kinds of AI chips on the market. One is to execute AI algorithms with traditional chips, such as CPU, DSP, FPGA, etc. The second is GPU + AI accelerator, which implements AI functions. The third type is customized. ASIC.

These three types of paths have different positioning due to 'genes'. Russell James, Imagination’s vice president of PowerVR vision and AI business, believes that the first category is for applications with less demanding performance requirements, such as face recognition, and accuracy requirements. Not high; the second category is for high-performance applications such as smart phones, smart surveillance, autopilot, etc. The third category of AISCs is specific to specific tasks, such as IoT domains. The reason is that the IoT domain requires correspondingly limited power consumption. The AI ​​task requires the ASIC with the highest performance and power consumption ratio. And the shipment volume in this area will be relatively large and worthy of attention.

These kinds of paths have their own advantages, but they are also flawed. Ke Chuan, regional market and business development director of Imagination China, believes that CPU efficiency is not high and speed is not fast under high-speed load; DSP is fast but R&D ecology is not complete; ASIC only The ability to perform fixed algorithm functions, scalability is not strong, and so optimistic about the overall advantages of GPU + AI accelerator performance, efficiency and power consumption.

Although Ke Chuan’s words are endorsed for his own IP, it is clear that an architectural AI chip cannot be used for all scenarios. Different scenarios require different kinds of technical support and need to be able to support the milliwatt level. Kilowatts of a variety of architecture.

Industry changes

The AI ​​craze struck, but from the development stage, it has not yet reached maturity.

Ke Chuan believes that the general industry is divided into four phases. First, the new technology comes to the forefront of institutions and companies to study and demonstrate, to find the possibility of industrialization; Second, the application of research stage to explore and solve practical problems; Third, rapid industrial development stage, At this time, many opportunities are also spawned. The fourth is to enter a mature period and become a relatively stable market, while the leading one is to establish a company with a Jedi advantage after the ebb. At present, the AI ​​is in the early stage of the third stage, namely the rapid development stage.

In this process, end-to-end AI functionality is more promising. Russell James said: 'AI is changing the industry, and the neural network is its core. Such processing has been mainly in the cloud, but due to delay issues, privacy issues and With increasing scalability requirements, edge AI processing has become very necessary.

In addition, the algorithm will gradually become open source, and it is necessary to quench the optimal solution for different applications. Russell James pointed out that the United States focuses on smart phones, autopilot and other aspects to improve AI performance, and China attaches great importance to intelligent monitoring, is a potential The huge market, while there are many opportunities in smart phones, automatic driving.

New IP

In several different paths, all the forces are trying their best to avoid weaknesses.

Imagination recently announced that PowerVR Series2NX, based on its Neural Network Accelerator (NNA) architecture, has introduced two neural network cores, the AX2185 and AX2145. It is important to understand that this architecture is the only solution that supports 16-bit to 4-bit width, which can be lower. Increased efficiency and real-time response with bandwidth and power consumption.

For different applications, these two types of IP cores have been greatly optimized in terms of performance and memory bandwidth. It is reported that the Series2NX AX2185 targets high-end smartphones, smart surveillance and the automotive market. The AX2185 has the advantage of having 8 full-width computing engines. , Each clock cycle can handle 2048 MAC (4.1 mega operations per second), while the power consumption is outstanding, achieving the highest performance per area. And the AX2145 is optimized for cost-sensitive devices to mid-range smart phones, digital The TV/Set-top box, smart camera and consumer security market are targeted for applications such as image recognition and machine vision.

The AI ​​chip competition is not only hardware performance, software ecology is also crucial. Russell James introduced, both of these cores fully support Android's neural network application programming interface, while Imagination provides a set of tools to simplify the development of AI applications. And for deployment and debugging and analysis, the machine learning framework can also use the Network Development Kit (NDK).

Russell James mentioned that these two AI-acceleration IPs have already been used by mobile phone and automotive manufacturers. More importantly, these IPs can also be adapted to CPUs, FPGAs, etc., but they have certain requirements for bandwidth delay and so on. It doesn't have to be 'matching' with the GPU. If these AI-accelerated IPs can be extended to other general-purpose chip areas, the path of the AI ​​chip may be variable.

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