Dr. Tu Fengbin, Ph.D., Department of Electronic Science and Technology, made an academic report at the conference
The International Conference on Computer Architecture is the top conference in the field of computer architecture. This conference received a total of 378 submissions and 64 papers. Tu Fengbin’s research paper is the only one signed by the first completion unit in China this year. Tsinghua University's Department of Microelectronics and Electronics, Professor Yin Shouyi is the author of this article. Tu Fengbin is the author of this article. The collaborators also include Professor Wei Shaojun and Professor Liu Leibo of the Department of Microelectronics and Electronics of Tsinghua University.
With the increasing size of neural networks in artificial intelligence applications, a large number of off-chip memory accesses to computing chips will cause huge system power consumption. Therefore, storage optimization is a core issue that must be solved in the design of artificial intelligence computing chips. The research team proposes a new acceleration framework for neural networks: The Neural Network Acceleration Framework for Data Lifetime Awareness (RANA). The RANA framework uses three layers of optimization techniques: Data-lifetime-aware training methods, hybrid computing models, and support. Refresh Optimized Enhanced Dynamic Random Access Memory (eDRAM) memory to optimize overall system energy consumption from three levels of training, scheduling, and architecture. Experimental results show that RANA framework can eliminate 99.7% of eDRAM refresh energy consumption overhead, while performance and The loss of precision is negligible. Compared to the traditional artificial intelligence computing chip using SRAM, the eDRAM-based computing chip using RANA framework can reduce 41.7% of off-chip memory access and 66.2% of system energy under the same area overhead. Consumption, make the artificial intelligence system's energy efficiency obtain the substantial increase.
Data Lifetime-Aware Neural Network Acceleration Framework (RANA)
The microelectronic and nanoelectronics reconfigurable computing team designed Thinker I, Thinker II, Thinker S, based on a reconfigurable architecture in recent years. It has attracted extensive attention from academia and industry. Reconfigurable Computing Team The research results have greatly improved the chip's energy efficiency from the perspective of storage optimization and hardware/software co-design, and opened up new directions for the evolution of the architecture of artificial intelligence computing chips.