Beijing, China, May 31st, 2018 - Synopsys (NASDAQ: SNPS), the world's largest provider of chip automation design solutions and the world's largest chip interface IP provider, global leader in information security and software quality, announced that Synopsys Design Platform has been certified by Samsung Electronics, the world's leading semiconductor technology company, to support Samsung's foundry's 8nm LPP (Low Power Plus) process. Synopsys Design Platform can be used for multiple graphical exposure lithography and full color of the 8LPP process. Perceived change technology, providing complete process support.
Synopsys's SiliconSmart® library characterization tool is the key to the development of the authentication process and reference process required for the underlying IP. The certification process also includes a set of scalable reference processes that are compatible with the Synopsys Lynx design system. The process includes automated scripting and design best practices. Users can obtain this reference flow through the Samsung Advanced Foundry Ecosystem (SAFETM) program.
Ryan Lee, vice president of marketing for Samsung Electronics’ OEM business, said: “Our 8LPP process can provide the most competitive process advantages before the industry switches to EUV (Earth-UV) lithography. Synopsys has always been our research and development at the new process node. First and foremost cooperation providers for energy generation. The combination of 8LPP's advantages in performance, power consumption, and logic gate density with the Synopsys Design Platform's high quality results and time advantage can enable our common customers to design and meet High-performance, most competitive 8LPP system-on-chip (SoC) products for low-power applications.
Michael Jackson, vice president of marketing and business development for the Synopsys Design Group, said: "Industry-leading customers have deployed the silicon-proven Synopsys Design Platform to design and produce faster, lower power 8LPP chips. Our reference design flow has passed The Samsung SAFE program has been widely used, allowing designers to quickly and confidently switch to Samsung's 8LPP process through the Synopsys Design Platform, taking full advantage of the resulting quality advantage of 8LPP's narrower metal spacing.
Based on the Armv8-A architecture of the 64-bit Arm Cortex-A53 processor, quality of results (QoR) can be optimized and process certified. The key tools and features of the Synopsys Design Platform 8LPP reference flow include: • IC CompilerTM II placement and routing: Multi-graphical exposure and color-aware physical implementation flow, with automated power supply and ground (PG) synthesis and built-in voltage drop sensing improvements. • Design Compiler® Graphical RTL Synthesis: With routing congestion improvement and physical boot capabilities, and IC Compiler II is closely related. • DFTMAXTM and TetraMAX® II testing: Based on FinFET, element sensing, and on-speed slew test based on timing margin, higher test quality can be achieved. • Formality® formal verification: UPF-based equivalence Checks, state transition verification. • IC Validator signoff physical verification: High-performance DRC signoff, LVS-aware short-circuit finder, signoff filling, pattern matching, and unique design-in-the-box verification in IC Compiler II Automatically repairs DRC, and metal fills to achieve accurate timing awareness. • PrimeTime® timing signoff: Pattern merging, using advanced waveform propagation (AWP) ultra-low voltage timing signoff, parametric on-chip variation (POCV) analysis, and perceptual layout rules such as Engineering Change Order (ECO) guidance. • StarRCTM extraction: multiple graphic exposures, Full color perception change and 3D FinFET modeling.
The Samsung SAFETM program now provides certified, scalable reference flows that are compatible with Synopsys' Lynx design systems. The Lynx Design System is a full-chip design environment that includes innovative automation and reporting capabilities to help designers implement and monitor their Design. It provides a production-level RTL-to-GDSII process that simplifies and automates many critical design implementation and verification tasks, enabling engineers to focus on achieving performance and design goals. The Samsung SAFETM program offers Samsung OEMs Extensively tested process design kits (PDKs) and reference flows (including design methods).