The USB 3.1 Gen.2 interface has been widely used, and the high bandwidth of 10Gbps is already abundant. However, there is no limit to technological progress. The new generation of USB 3.2 standard specifications was officially announced at the end of September 2017. Synopsys is now demonstrating USB 3.2 for the first time.
The USB 3.2 device and host of this demonstration are based on the HAPS-80 FPGA hardware prototype platform. The USB PHY physical layer is manufactured using the FinFET process. Each channel has a bandwidth of 10Gbps, and the dual channel strength reaches the required 20Gbps (2.5GB/s). USB 3.1 Gen.2 has doubled.
The HAPS platform connects to a Linux PC through the PCI-E bus. The device is configured as a mass storage device, such as a USB 3.2 SSD, a USB 3.2 U disk, and to reduce latency, a small amount of RAM on the FPGA is used as the memory.
The host platform is also similar, affixed to a PHY motherboard, where HAPS is connected to the Windows PC through the PCI-E data cable, and the FPGA motherboard is connected to the PC as a USB 3.2 xHCI host expansion card. The system uses a standard Windows driver.
The speed in the demonstration is 1.6GB/s , compared with the standard limit only played about 2/3 of the power, there is much potential to be excavated.
In addition, The USB 3.2 era interface style will be unified for more convenient, more flexible, more powerful Type-C , Type-A, which has been circulating for many years, will gradually be withdrawn from the stage of history.
However, as with every previous standard upgrade, the popularity of USB 3.2 will take a long time. It is expected that relevant equipment will be available next year. In addition, Intel and AMD have only recently supported USB 3.1 Gen.2. The integration of USB 3.2 into the platform will be farther away. The initial stage will be the third-party master chip.
