Synopsys IC Validator Receives GLOBALFOUNDRIES 14LPP Physical Validation Signoff Certification

May 23, 2018, Beijing, China - The world's largest chip automation design solution provider and the world's largest chip interface IP provider, Synopsys (NASDAQ: SNPS), a global leader in information security and software quality, announced that The Synopsys IC Validator tool has been certified by GLOBALFOUNDRIES (GF) and will be used for physical verification of GF 14LPP process technology Signoff. With this Signoff certification, design engineers can achieve high levels of manufacturability with the rapidity and scalability of IC Validator And maximum production capacity. At present, GF can provide a variety of certified operating set, including DRC, LVS and metal filling technology files.

Jai Durgam, VP of customer design and implementation at GLOBALFOUNDRIES, said: 'The IC Validator Signoff certification is an important step in supporting our mutual customers to physically verify Signoff. Synopsys works closely with us on 14LPP process technology to provide IC Validator with extensive tool certification and Runsets certification. Our foundry customers can now maximize the high performance and power efficiency benefits of 14LPP process technology through the use of IC Validator's rapid analysis capabilities. In addition, we are actively expanding the application of IC Validator to all Signoff certification for advanced processes. 'IC Validator is a key component of the Synopsys Design Platform and a comprehensive and highly scalable suite of physical verification tools including DRC, LVS, programmable electronic rule checking (PERC), virtual metal padding and DFM enhancements. IC Validator is designed to achieve high performance and scalability through the use of intelligent memory-aware load scheduling and balancing technology to maximize the utilization of mainstream hardware. Multithreading and distributed processing can be used on multiple machines. To provide an extension to one More scalability benefits of the CPU.

According to Christen Decoin, Senior Business Development Director, Synopsys Design Division, “The complexity of advanced node manufacturing poses great challenges for design engineers to deliver on schedule. Working closely with GLOBALFOUNDRIES ensures that design engineers can access performance optimized runtimes in time. These runsets and ICs The scalability of Validator's massively parallel architecture works together to provide design engineers with a fast and accurate physical verification Signoff path.

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