This article was reprinted with permission from Superpower.com.
We often hear at a mobile phone conference site that the '×× processor is manufactured using the most advanced 10nm process'. So what does this 10nm mean? What is the importance of nano-processes for CPUs and SoCs? What is the relationship between transistor, FinFET and EUV?
The birth process of a CPU, where the seventh step of UV exposure is the most important lithography technology, and the lithography process is the most direct technology in the manufacturing process of integrated circuits to reflect the advanced degree of its technology, in which the resolution of the lithography technology refers to The minimum line size that the lithography system can resolve and process determines the minimum feature size of the transistor in the CPU.
According to the relevant regulations in the ITRS "International Semiconductor Technology Blueprint", the 16nm, 14nm, and 10nm that we usually talk about are used to describe the node algebra of the semiconductor process, and it should be on different semiconductor components. The objects described may be different. Differently, for example, in DRAM, the Half-Pitch half-pitch length may be described as the half-pitch half-pitch length of the minimum allowable pitch value between two metal lines in the DRAM Cell; when used on the CPU, the CPU may be described as the CPU. The minimum gate width in the transistor.
In general, the ××nm process describes the accuracy of the process scale, but it does not refer to the feature size of a specific structure in a semiconductor device, but the minimum size of the process accuracy. Here we mainly discuss It is about the process of the CPU, because the process has an important role in terms of CPU performance, power consumption, and heat generation. The process change has a huge effect on CPU performance. As we mentioned before, 14nm is usually used to Describe the gate width of the transistor.
Why use the gate width instead of the other line width to characterize the process node?
This is mainly related to the transistor structure problem. Generally speaking, the internal logic gate circuit of the CPU uses the MosFET. It has three electrodes, a gate, a source, a drain, and a gate and a source. The voltage difference between the poles can control the current flowing from the source to the drain, so the gate plays a controlling role.
At the same time, the characteristics such as the transistor electron mobility are completely dependent on the doping ions and the production process, basically cannot be moved, but the length and width ratio of the transistor gate can still be used as a matter of fact. The smaller the gate width, the electrons may flow through the crystal substrate from the negative electrode to the positive electrode, resulting in leakage, and the leakage problem will lead to a rise in static power consumption.
Therefore, the effect of the gate line width is very important. The gate line width is usually the most important parameter for the design of VLSI circuits, and it is therefore referred to as the node of the semiconductor process. This is the traditional process specification.
So what does this mean is that the smaller the process, the better?
Indeed, you think, the smaller the line width, the smaller the size of a single transistor. The smaller the die size of the CPU, the more wafer die can be produced on the same wafer. This increases vendor revenue (more chips). In turn, you can also integrate more transistors with the same die area, and CPU performance will improve (of course, this is not absolute).
Secondly, as the gate line width becomes smaller, the operating voltage will be reduced accordingly, and the power consumption of the CPU will also be reduced. In addition, under more advanced processes, the transistor cut-off frequency will perform better and the CPU will naturally work. At higher frequencies. So we often see So-SoCs, CPUs say that we have adopted a more advanced 10nm, power consumption has decreased by ××%, frequency has increased by ××%, and performance has increased by ××%.
Taiwan Semiconductor Manufacturing Co., Ltd. has been mass-produced for 10nm for a long time. Intel has yet to ship. Intel's invincible process is not enough.
In the past few years, Intel entered the 14nm era from 22nm. Everyone is saying that Intel is at least three to five years ahead of other manufacturers in terms of process technology. However, it has not lasted long. We found that Intel 14nm actually polished again and again, from Skylake. (14nm), Kaby Lake (14nm+), Coffee Lake (14nm++), still used after three generations, it is said that there will be 14nm+++, originally said that a good 10nm encounters a lot of technical problems and is difficult to produce.
Looking back at rival TSMC, Samsung took a hitch on the OEM road, catching up with Intel's progress on the 16/14nm node. Surprisingly, Taiwan Semiconductor Manufacturing Co., Samsung's 10nm process mass production was far earlier than Intel's. Related products (such as Qualcomm Xiaolong 835) It has been sold on the market for a full year. TSMC even mass-produced a 7nm chip this year. What is going on here?
The general public believes that 10nm is definitely more advanced than 14nm, and 12nm is better than 14nm. When Intel was about to be swamped by negative public opinion, Intel broke the 'mysteries' behind the number of nanometer process technology because TSMC and Samsung's process numbers went through different The degree of 'beautification' is a little clever in terms of naming, that is, 'digital' suppression. Although Intel lost in 'digital', Intel is actually superior to some key technical parameters in various aspects of the process. This phenomenon has occurred in 14nm, and the ××nm process has already begun to break away from the original category. Everyone starts to falsify.
In the 14nm era, Intel has already played a behind-the-scenes secret
Techinsights also made a comparison, Intel 14nm is indeed better than Samsung's 14nm LPE
Intel said that the line width only represents the process node, but to measure the quality of the process, Gate Pitch gate spacing, Fin Pitc fin spacing, Fin Pitch minimum metal spacing, Logic Cell Height logic cell height parameters more reference significance. Mark Bohr, Senior Fellow of Intel's Processor Architecture and Integration Division, proposed to measure the semiconductor process level with Transistor Density transistor density, and proposed the following formula:
For example, at the Technology and Manufacturing Day held by Intel in September last year, it unveiled three technical parameters related to the 10nm process. We have seen that Intel has suspended the other two in these key technical indicators, such as Intel's 10nm light. The fins produced by the engraved technology have smaller gate spacings (note that Intel has published interval comparisons, not line widths, and it makes more sense). Therefore, the density of transistors is almost twice that of TSMC, which is twice as high as Samsung. Millions of transistors per millimeter, while maintaining the fine tradition of low logic cell height, has an advantage in 3D stacking.
Recently, Semiwiki reported on Samsung's 10nm, 8nm and 7nm process transistor densities. The transistor densities of its 10/8/7nm process are 55.10/64.4/101.23 MTr/mm2, respectively. As can be seen, Samsung's 7nm process is in terms of transistor density. Only to pursue the Intel 10nm, who is playing tricks, you do not know, right?
Where is the limit of that process?
When the process is lower than 20nm, because the silicon dioxide insulating layer is too thin, only a few atoms are so thick, then this time is very unstable for the transistor, which will cause electrons to randomly pass through the barrier and lead to leakage, resulting in chip work. Increased consumption. However, this is still a minor problem. Intel has developed high-dielectric-constant films and metal gate ICs, as well as the familiar FinFET fin field-effect transistor structure. By increasing the surface area of the insulating layer to increase the capacitance, the leakage is reduced. The current size problem. At the same time, in order to produce a 7nm line width, the industry consensus is to use EUV EUV as a lithography source, with a small number of exposures, not to overcome the diffraction proximity effect of optical proximity correction features, but there are still a lot of problems, therefore EUV lithography technology is not yet fully mature.
When the process progresses to 7nm, semiconductor companies are even less calm, because on silicon-based semiconductors, the line width of transistors has dropped to 7nm, and an inevitable problem has occurred, the famous quantum tunneling effect.
In classical physics, when the energy of a macroscopic particle is less than the height of a barrier, it is impossible for this particle to cross this barrier, but for microscopic particles, there is wave-particle duality at this time, and the magical quantum effect appears, even if If the energy is lower than the barrier height, there is still a certain probability that it can break through the barrier. This will cause a big problem. This electron has passed in the end. If it is not detected, the logic gate will output 0 or 1, the answer is unknown, then the CPU It will not work, so we must prevent this problem from happening.
Intel, TSMC, Samsung and other semiconductor manufacturing frontier companies have conducted research on this issue, there are still some measures to prevent the emergence of quantum tunneling effect. For silicon-based semiconductors, Intel is the prospect of the process limit is 5nm or 3nm; Samsung's words Follow-up will be 8/7/6/5/4nm LPP process, and in 4nm will introduce Multi Bridge Channel FET structure (abbreviated MBCFET, multi-channel field effect transistor), unique GAAFET (logic gate surround field effect transistor) technology, use two Nano-lamellae overcome the limitations of physical expansion and FinFET architecture.
The reports on the media below 3nm technology are not based on silicon oxide, but rather new composite semiconductor materials such as graphene, and all of them are breakthroughs in laboratory technology and cannot be mass-produced in a short time. However, finding new materials instead of silicon production Low-level transistors are one of the most effective solutions.
The False and Reality Behind Nano-Process Process
After reading the full text, you will know that the current semiconductor process called 10nm, 7nm has deviated from the original category, is no longer a strict sense of line width, 16nm 'optimized' can be called 12nm, 10nm 'optimized' can also be called 8nm. As Moore's Law advocates Of course, Intel's Intel is, of course, overwhelmed by criticism of Samsung's 'digital beautification' behavior. Actually, from the perspective of transistor density parameters, Samsung's 7nm Intel 10nm, it seems that Intel's 10nm dystocia is also excusable, The goal was set too high, but it was won by a friendly business name. The general public believed the manufacturer's side because they didn't understand the truth of the manufacturing process. Intel's manufacturing process technology is not so bad, it is still in the world's leading position. status.
