Arm pointed out that TSMC's 22nm ULP/ULL process is optimized for mainstream operations and IoT devices. It not only improves the performance of the SoC based on the Arm architecture, but also significantly reduces compared to TSMC's previous generation 28nm HPC+ process platform. Power consumption and chip area.
Gus Yeung, general manager of Arm's physical design business group, said that this next-generation process technology can add more features with lower power consumption and smaller area, combined with Artisan physical IP and TSMC's 22-nm ULP/ULL process platform. There are advantages in design and manufacturing costs. Both parties will provide each other's partners with immediate performance per milliwatt of computing performance, as well as savings in chip area benefits.
Arm further pointed out that Artisan's physical IP using TSMC's 22nm ULP/ULL process technology, including a fab-sponsored memory compiler, optimizes the need for low-leakage and low-power consumption for next-generation network terminal computing devices. State. These compilers also come with a library of ultra-high-density and high-performance physical IP standard components, including a power management kit, a thick gate oxide library, etc., to help optimize low-leakage power consumption. In addition, a general-purpose type is also provided. I/O solution to ensure maximum performance, power consumption, and area (PPA) optimization.
Suk Lee, senior director of TSMC's Design and Construction Marketing Division, pointed out that Artisan's physical IP has allowed TSMC to accelerate its tape-out schedule, target mainstream IoT and mobile devices, and accelerate the listing of these industry-leading SoCs. Continued TSMC and Arm’s Based on the successful cooperation of the 28-nm HPC+ platform, TSMC and Arm have teamed up to significantly reduce power consumption and area, providing opportunities for each other's common chip design partners, and presenting more complete terminal computing experience in more devices.
Arm pointed out that under the active integration process with TSMC's 22-nanometer ULP/ULL process technology, it is ensured that the chip design partners that meet Arm's and TSMC's common design partners can complete the relevant design finalization in the second half of 2018.