This article was reprinted with permission from Superpower.com.
Taiwan Semiconductor Manufacturing Co., Ltd. (TSMC) has recently been very enthusiastic. The first-generation 7nm process has entered the mass production stage. At the recent TSMC Technology Symposium technical conference, a revolutionary process technology called Wafer-on-Wafer (WoW, stacked wafers) was proposed. , Just like the 3D NAND flash multi-layer stacking, the two layers of Die are vertically stacked in a mirrored manner, which is expected to be used to produce graphics GPUs, creating larger GPUs for transistors.
This front-end product has developed similar technologies Chip on Wafer on Substrate (CoWoS) and Integrated Fan-Out (InFO). These two technologies are currently used in various products. For example, Intel and Xilinx FPGA chips use CoWos. , Apple's A Series SoC uses InFO.
This time, the largest application scenario of WoW will likely be on the GPU core, which can increase the number of transistors without increasing the GPU core area or using a smaller process process, thereby improving the graphics performance.
According to the blog of the famous EDA manufacturer Cadence, the WoW technology connects the upper and lower die through a 10μm silicon piercing method, so that more die can be stacked in the vertical direction, which also means delayed communication between the die and reduced earth. Introduce more cores.
However, the biggest problem with current WoW technology is that the process requirements are very high, and the die must be aligned accurately and without any problems. If one of the die is not problematic, one of the die will not work, and the entire package will be scrapped. Therefore, the yield rate is relatively low and the production cost is high.
Therefore, it is appropriate to add WoW to the already mature 16nm process, but TSMC's target is indeed applied in the future 7/5nm.
Cadence and TSMC announced that they have passed the WoW Reference Flow 1.0 standard certification in Cadence tools.
