Cadence recently announced the industry's first DDR5 memory IP interface chip, including the controller and PHY physical layer, manufactured using TSMC 7nm process, operating at a frequency of 4400MHz, Micron also presented its own DDR5 memory particles.
JEDEC is currently developing a standard specification for DDR5 memory, which is expected to be completed this summer. , So the current is still some basic research, DDR5 memory in the end have to look like what have to wait.
The data rate of Cadence DDR5 memory controller and physical layer is 4400MT/s, timing CL42, and Micron 8Gb DDR5 memory particle prototype, voltage is only 1.1V (DDR4 1.2V), fluctuation range ±0.033V.
With these foundations, SoC chip manufacturers can begin to design and integrate DDR5 memory subsystems, paving the way for the future.
Just as DDR4 memory frequency goes from 2133MHz to 3200MHz (JEDEC standard), 4400MHz is only the beginning for DDR5. It is expected that it will eventually reach around 6400MHz.
In addition to frequency, DDR5 memory is more valued than it is large capacity. , Allows the addition of internal ECC to manufacture 16Gb, 32Gb particles.
DDR5 memory will still follow the layout of 288 pins, but the specific design will certainly be different from DDR4, and there are two independent 32-bit IO channels, the overall architecture will be very different.
Other DDR5 improvements will also include: better channel utilization, integrated voltage regulators, high-end modules to support power management, and more.
Cadence expects that the first DDR5 memory system will be available in 2019, and then quickly become popular. By 2022, it will achieve about 25% penetration rate.
