Wafer-on-Wafer (WoW, Stacked Wafer) technology is in contact with each other through the use of 10 μm holes that form through silicon vias (TSVs). Cadence of TSMC explains that Wafer-on-Wafer (WoW, stacked wafers) The design can be placed on an interposer, routing a connection to another connection, creating a double-crystal cube. Even more than two wafers can be vertically stacked using the WoW method.
This technology will allow more cores to be tucked into a single package, and means that each wafer can communicate with each other very quickly and with minimal delay. Of particular interest is that manufacturers can use the WoW approach to both The GPU is placed on a card and released as a product update to create basically two GPUs without displaying it as an operating system's multi-GPU setup.
The biggest problem with WoW now is wafer yield. When they are bonded together, if only one wafer is broken, then even if both wafers are fine, they must be discarded. This means that the process needs to be High-yield production nodes are used on the production node, such as TSMC's 16-nanometer process, to reduce costs. However, the company's goal is to use WoW technology at future 7nm and 5nm manufacturing process nodes.
