DDR4 memory is still the absolute mainstream, and it has been continuously tapping into potentials. The frequency has already exceeded 5GHz, but the next-generation DDR5 is just around the corner. Cadence today announced the new progress of DDR5, both in terms of technology and frequency.
At present, the JEDEC standard organization is studying the next-generation DDR5 memory specification, and there is already a preliminary version. Cadence took out the first DDR5 IP physical layer interface chip for the new specification.
The test chip is manufactured using TSMC's 7nm process, and the data rate can reach 4400MT/s, which is the frequency up to 4400MHz, which is as much as 37.5% faster than the fastest commercially available DDR4-3200.
In order to support the validation and collaboration of the Cadence DDR5 PHY physical layer, Micron also provided it with a preliminary version of the DDR5 memory engineering prototype.
Prior to this, Rambus also mentioned DDR5 IP under the 7nm process, and it is expected that DDR5 memory will not be commercially available until 2020, and the first ones will naturally be servers and data centers, and the consumer level will be even lower.
It is worth mentioning that AMD has promised that the current AM4 interface will continue to support it until 2020, when it is very likely that it will replace the new interface and add support for DDR5.
