Open source instruction integration long-term potential | Crystal core new architecture into RISC-V

Jingxin Announces the New Generation of AndeStar V5 Processor Architecture, Supports 64-bit Processors, and RISC-V Instruction Set Architecture, which is currently focused on by the industry, enabling the open, streamlined, modular, and scalable RISC-V architecture to enter the mainstream System-on-a-chip (SoC) applications, in addition to expanding the RISC-V ecosystem, also help SoC design companies reduce time-to-market.

According to Lin Zhiming, general manager of Jingxin Technology, RISC-V is an emerging open source processor infrastructure technology/standard featuring features such as a simplified, modularized instruction set, easy/allowable expansion to promote the rapid growth of ecosystems. RISC-V Foundation, like Google, Microsoft, Qualcomm, MediaTek, etc.

Lin Zhiming further explained that for the IC design companies, the construction of the ecosystem is the key to development, and the recently visible RISC-V ecosystem is continuously growing. Looking at the future growth potential of RISC-V, the company has not only become a RISC-V fund. Founding members, developed a new generation of V5 architecture based on RISC-V, incorporated RISC-V into mainstream commercial CPU IP design, and expanded RISC-V ecosystem.

It is reported that AndeStar V5 not only fully incorporates RISC-V compatibility, but also has a variety of expansion framework of crystal core. Including: Crystal core original instruction set, can reduce program code by 10%, reduce chip code storage cost; Customized Instruction (ACE) allows customers to specify application acceleration instructions. Optimized interrupt handling can significantly reduce real-time interrupt processing time; and StackSafe, a hardware protection mechanism for the program stack, improves debug efficiency.

The V5-based 32-bit N25 and 64-bit NX25 AndesCore processors, operating under the TSMC 28nm HPC process, can operate at frequencies exceeding 1GHz, providing high-performance, logic gates of at least 2.8 DMIPS/MHz and 3.4 CoreMark/MHz. The number can be as low as 30K and 50K respectively. Therefore, N25 and NX25 are very suitable for various applications requiring high-speed control such as network, storage and artificial intelligence (AI).

RISC-V's ecosystem is rapidly rising. Lin Zhiming mentioned that the current development of RISC-V is still in its infancy, but its growth is very fast. The relationship between RISC-V and Arm architecture in the future may be like Android and Android. Like ios, both have champions and they also have their own huge ecosystem.