Over the past ten years, open source software has become the best catalyst in the field of technology. Today, the power of open source has brought about free development, and the resulting community has also gained a foothold in the hardware world. For these reasons, RISC-V has gained a lot of popularity. This article introduces the RISC-V instruction set (ISA) architecture and how to rewrite the rules of the processor ecology in the Internet of Things (IoT) era.
What is RISC-V?
RISC-V is an open instruction set architecture originally developed by the Department of Computer Science at the University of California, Berkeley, based primarily on the popular reduced instruction set computing (RISC) principle. , Just like ARM, MIPS and other common commercial processor architectures.
RISC-V began molding in 2010 and has now grown into a huge global collaboration program spanning multiple universities and industries. The non-profit RISC-V Foundation has provided consistency. It not only guides the underlying ISA specification, but also plays the role of a marketing engine to promote the RISC-V approach.
What needs to be clarified is the RISC-V instruction set architecture. As its name implies, it is an instruction set architecture specification, not a specific processor design. Starting from the open source instruction set architecture, many academic and industrial teams have created many Different processor designs, but essentially all using the same language. A quick look at the RISC-V Foundation website, you can see that a lot of processor implementations are shown above, from the complete open source of Rocket, Orca and PULPino Processor design, to companies that produce commercial processor cores such as SiFive, Codasip, Andes and Cortus.
These contemporary processors have a wide range of implementations. From simple IoT processors to application processors running Linux, all are based on a common set of instructions, reflecting the key advantages of RISC-V over closed commercial ISAs. Differentiation and freedom of choice, and the ability to replace processor vendors without suffering the pain of product re-architecture.
Free, so there must be a risk?
At this point, it is prudent to look at the actual situation and look at the factors that affect processor choice in new product designs. Like most design decisions, it involves many technical and commercial factors, some are based on hard indicators, and others are based on difficulties. Quantitative aspects.
The technical indicators are self-evident: Does the processor include enough horsepower? Support the scalability of subsequent products? Does it match power packets? Does it meet the required security level? Is there a friendly and familiar software development/debugging environment? • Can a user inherit legacy code libraries, etc. Commercial standards must consider costs, such as area (including number of gates and memory size), royalties, and overall authorization costs. It also takes into account other business factors, including suppliers. Lockdown, guarantee and compensation, business reporting obligations, legal rights to make changes, etc.
Considering all of these factors, most designers tend to adopt a 'safe' option, usually using a proprietary commercial processor, and often bind to a previously used series. However, at the strategic level, many companies are Increasingly restrictive but powerful commercial processor IP vendors are uneasy. People are eager to have more commercial freedom and break the lockout of closed instruction sets. This is not only meaningful in terms of licensing and copyright royalties, but also conducive to differences. Turning.
This demand makes RISC-V set sail. The RISC-V open source instruction set architecture provides chip companies with a realistic choice to go beyond common business options and avoid overly strategic risks like Linux, FreeRTOS and many others. The source-coded real-time operating system (RTOS) is today's irrefutable alternative to commercial operating systems (OS). This is especially true for small embedded processors used on consumer IoT devices. Many well-known Tier 1 companies, including Western Digital (WD) and Nvidia, have publicly announced the intentions of their own company and even started large-scale production. In addition, many more companies are evaluating RISC. -V, some of them even secretly start advanced design.
For example, CEVA RivieraWaves' Wi-Fi and Bluetooth IP product design. Attracted by the potential of RISC-V, these communication technologies require a small processor to perform protocol stacking. The goal is to create a pre-integrated reference platform for customers to choose freely. Processors. Because the architecture of IP is designed for ultra-low power operation, even the advanced wireless network (Wi-Fi) configuration, the demand for processor horsepower is also very mild.
In short, we need a small number of logic gates, high energy efficiency, a mature processor, and a familiar commercial-grade software development environment that can result in compact code that saves chip area. The processor design must be easy to deploy ( Full speed execution) on FPGAs and ASICs/ASSPs, but also must have a regulatory framework that is compatible with our authorized IP services.
For example, CEVA chose the RISC-V processor core with 20K gates, which can achieve a good performance of 2.44 Coremark/MHz, and is in perfect agreement with the hardware requirements. According to internal performance benchmarks and code density test results, it has been achieved. The same level as the best processor in its class. It is also important that according to our experience, the workload required to migrate a complete system to RISC-V is very small.
Taking the more complex Wi-Fi platform as an example, replacing the commercial processor with an embedded RISC-V processor takes only one week to complete the integration, simulate and create a new FPGA binary file, complete The RivieraWaves Wi-Fi Display Platform. In addition, existing protocol software that has been developed and deployed for many years on several different commercial processors can be ported to the RISC-V platform in two weeks, including porting, testing and System-level verification. This is not surprising, thanks to the familiar GNU GCC/GDB and LLVM compiler/debugger environment.
In general, this project was a major success. RISC-V truly fulfilled its promise.