Although Intel processors have made slow progress in the consumer-grade field in recent years, Intel still has a lot of hard work in the server and data center markets, and it will be even harder.
The Power Stamp Alliance (PSA) Alliance, which aims to convert low-voltage, high-current applications to 48-V input busbars, has played a role as a 'pig-mate' and has revealed some of Intel’s next-generation Xeon platforms. It looks really powerful. .
Intel's current Xeon scalable platform (platinum/gold/silver/brass) based on the 14nm Skylake architecture, up to 28 cores, today Upgrades its next-generation product architecture to Cascade Lake (The Kaby Lake/Coffee Lake jumps directly from the waistcoat) and Intel has previously publicly announced it.
Not surprisingly, the Cascade Lake platform will use a 10nm process, and according to the PSA's exposure, It will continue the current LGA3647 package interface, maintain backward compatibility, thermal design power consumption is still the highest control at 165W.
And then the architecture is Ice Lake. Based on the second generation 10nm+ process, the release time is 2018/2019 (if it is too late at the end of this year), and the package interface is changed to LGA4189, which is backwards compatible through the adapter. Design power consumption up to 230W.
4189 contacts/pins will make it the largest processor interface ever Nearly 15% more than LGA3647, AMD TR4/SP3r2 is only 4094 contacts/pins.
So many contacts/pins are obviously prepared for more and more functions, such as DDR4 memory support will be upgraded from six-channel to eight-channel, comparable to AMD EPYC, with up to 16 memories per channel, and possible integration of OmniPath high-speed channels and on-board FPGAs.
