1.June: TSMC's 7nm mass production, Zhang Zhongmou retires;
According to the micro-network news, the Economist wrote that TSMC will kill Intel and become the world's strongest wafer fab. The analysis of its two key wins lies in its investment in R&D and OEM mode.
Zhang Zhongmou is about to retire. In the future, TSMC will adopt a dual-CEO parallel leadership system and hand over to Liu Deyin and Wei Zhejia. The Economist reports that in the month of Zhang Zhongmou’s retirement in June, TSMC will ship the most advanced process semiconductors and grab the world’s most The throne of strong chips, Intel became the second child.
The report pointed out that Intel follows the 'Moore's Law'. In the past, Intel took the lead in process technology. Currently, the chip production technology is 10 nanometers, and TSMC is ahead of 7 nanometers. The technical advantages are also reflected in the stock price. TSMC's 2017 market value exceeded that of Intel for the first time in 2017.
How TSMC can squeeze out Intel has always been the focus of the market. Two major reasons are analyzed. One is that TSMC has invested nearly 3 billion U.S. dollars in research and development expenses far more than its peers; the other is the advantage of OEM mode. Intel’s strength is the computer chip. Samsung is good at smart phone chips, TSMC is the two pass kill, and even eat 90% of the super-mining chip.
According to the report, TSMC has customers such as Apple and blessing, which contributes to stable revenue, and continues to invest in research and development to upgrade process technology, drive a virtuous cycle of growth in operations, and leave competitors behind.
2. The semiconductor boom Q1 falls to the end of this season is expected to return to temperature;
With the gradual recovery of mobile phone market demand, the semiconductor industry is expected to bottom in the first quarter, and the second quarter will be able to gradually return to warmer. The consumer IC plant is expected to leap up due to the timing of the traditional peak season and will be the largest growth. Ethnic group.
The first quarter was the traditional off-season of the semiconductor industry. In the first quarter of this year, the weak demand in the mobile phone market, including wafer foundry TSMC, MediaTek and other semiconductor giants faced downward pressure in the first quarter.
Among them, TSMC's first quarter revenue will be about 8.4 billion to 8.5 billion US dollars, will reduce the quarter by 8%; MediaTek's first quarter revenue will be about NT 48.3 billion to 53.2 billion yuan, quarterly reduction of 12% to 20%.
With mills and OPPOs and other branded mobile phone manufacturers in China launching new machines, the industry is optimistic that the mobile phone market demand will gradually recover. MediaTek P60 is expected to be hot, wireless network and power management chip shipments will also grow simultaneously, will drive the The second-quarter results will rebound and will increase by 15% in the quarter.
In addition to the recovery of mobile phone market demand, Bit Continental will launch an Ethercoin mining special application chip (ASIC). The industry is optimistic that it will be able to instigate the performance of TSMC. In the second quarter, the operation is expected to recover simultaneously.
The consumer IC market has obvious differences during the peak season. The first quarter is the traditional off-season, usually the bottom of the manufacturer's one-year operation. The second quarter is the traditional peak season, and the vendor operations are mostly leaping growth, which is the peak annual performance.
This year, the second quarter of consumer IC plant operations will continue the trend of high growth, quarterly revenue is expected to increase by more than 20% quarterly, and some manufacturers' second quarter results do not rule out the opportunity to increase by 50% quarterly, will be the second semiconductor factory The largest growing group in the quarter.
3. Attack the global NAND Flash market, Micron announced the construction of its third plant in Singapore;
There is still a gap in the supply of NAND Flash flash memory in the market, which has led to the maintenance of high prices, including international giants Samsung, SK hynix, Toshiba, and Chinese manufacturers, Changjiang Storage, which have announced expansion to increase production capacity. On the 7th, Micron announced that it will expand production to make up for the shortfall in the market.
Micron pointed out that following the existing NAND Flash flash memory plant Fab 10N, Fab 10X in Singapore, the third NAND Flash flash memory plant will be built locally. The new plant covers an area of approximately 165,000 square meters. Completed around mid-2019, production began in the fourth quarter of 2019.
However, Micron did not announce the specific type of NAND Flash flash memory type and production capacity of the new plant. However, according to external predictions, the type of NAND Flash flash memory product that will be put into production should be under the existing 64-layer stacking flash memory. Generation products.
In addition, in addition to Micron’s announcement that it will build its third NAND Flash flash memory plant in Singapore, Micron also stated that it will expand the current R&D scale in Singapore, which will increase the total number of local employees from the current 7,500 to 1 More than 10,000 people.
In addition to the development of Micron's NAND Flash flash memory, it is worth mentioning that, in the DRAM area, not long ago, the Micron's Taichung plant also suffered from a nitrogen problem due to a circuit problem in the nitrogen supply equipment. This caused a nitrogen supply failure and affected some products. In this regard, Micron CEO Sanjay Mehrotra has also confirmed the matter in the previous law meeting.
Sanjay Mehrotra stated that the impending obstruction of nitrogen supply would cause the company to reduce its DRAM output by 2% to 3% in the quarter. And Micron has sent relevant faulty equipment to the United States for repairs and returned to the factory a few days ago, and in April, Started to return to production. Technews
4. PS5 technical specifications leaked, adopting 7-nanometer process Navi GPU;
According to foreign media sources, the game developer development kit revealed that the PlayStation 5 console will use the Zen architecture's 8-core CPU, as well as the Navi architecture-based GPU that has not yet announced details.
It is estimated that the new Navi architecture GPU performance will reach 50TFLOP half-precision and 30TFLOP single-precision, supporting 16 to 128 GB of Nexgen memory. AMD said that although Raja Koduri, an important engineer leading the development of graphics cards, left, Navi architecture products are still going well. It is expected that the actual product application will be released in 2019 and TSMC will adopt the 7-nanometer process, which will also be the last generation of the GCN display.
The PS5's eight-core Zen CPU clocks from 3.4 to 4.1 GHz, and the overall performance far exceeds the current strongest 6TFLOP and Xbox One X. of 2.3 GHz processors. And recent SemiAccurate media claims that it is within the news that the PS5 will likely be earlier in 2018. It was released at the end of the year or 2019, but Michael Pacher, an industry analyst, thinks it is unlikely. The odds of being released this year are almost 0, and the probability of being released in 2019 is only 25%. It is only reasonable to speculate in 2020.
Michael Pacher pointed out that Sony is unlikely to release the PS5 until the PS4 sales boom slows, and it is not unexpected until late in 2021. But in the future, Sony will phase out other PS4 models, leaving only Pro, and will Extend the lifespan of PS4 games and cut prices again. He emphasized that Sony believes that consumers may not pay for high performance, and that the higher specification Xbox one X is not as bright as sales, so the price of PS5 in the future is estimated to be less than US$500. .
Although Michael Pacher's past predictions are not entirely correct, the current market does indeed believe that releasing the PS5 at the end of 2018 is too early to threaten the current PS4 revenue. There is also news that the PS5 will focus on optimizing the VR experience, and In fact, there is still some time in the city, but Sony may indeed complete the PS5 prototype this year and publish technical details. Technews
5. Experts share: What are the challenges of achieving 3nm?
3nm test chip
In October 2015, Cadence and imec announced the successful tapeout of the world's first 5nm chip. At the end of February this year, Cadence and imec jointly announced that the next-generation 3nm test chip has been successfully taped out. This design adopts the Cadence GenusTM integrated solution and InnovusTM. Design and implementation system, test chip adopts industry-standard 64-bit CPU design, built-in custom 3nm standard cell library. The minimum metal wiring pitch of the chip is only 21nm. 21nm this number may not be intuitive, if the benchmark single exposure If the 193nm lithography layout pitch does not exceed 80nm, then how advanced this design scheme is can be seen. Similar to the earlier 5nm test chip, the 3nm chip used EUV and 193i multiple exposure double hypotheses when studying the PPA target. The solution. To implement component interconnections, variables and resistors (especially contacts/vias) are the biggest challenges. For details, please refer to an IEDM short course I posted a few months ago: After 5nm One of the goals of the test chip is to measure and improve the variables. EUV technology for 3nm chips requires double exposure because the EUV 'light' has a wavelength of 13.5nm. EUV can also be used to test new pathways, as well as new materials such as cobalt and antimony.
Collaborative optimization of design technologies
In the past few decades, the expansion of process technology and the richness of design rules for content libraries have been the driving factors for the development of Moore's Law; however, nowadays, it is not enough to rely on process expansion alone. The size of standard cell libraries must be greatly reduced, and cabling The number of channels must also be reduced. To achieve this goal, we need to add additional process features that do not require direct scaling, such as active gate contact. In particular, we can add super vias to the MEOL to achieve optimization. Super vias are through holes that span more than one layer, occupy a minimum area, and do not require metal structures in the middle layer.
The biggest advantage of active on-gate contact (COAG) is that there is no need to place a separate gate contact outside the gate. Intel announced at the IEDM in December that its 10nm process (equivalent to what the fab claims The 7nm process) uses active gate contacts. I expect that the 5nm and 3nm processes will fully utilize active gate contacts, and some second-generation 7nm processes may also use this technology.
In addition to the interaction between the process and the unit design, layout and routing are also important. For example, under certain conditions, although free cabling channels will increase the cell area, the use of free cabling channels between cells can reduce the cabling area. The improvement of the wiring efficiency can completely offset the increase in cell area caused by the idle wiring channels. Cadence