In October 2015, Cadence and imec announced the successful tapeout of the world's first 5nm chip. At the end of February this year, Cadence and imec jointly announced that the next-generation 3nm test chip has been successfully taped out. This design adopts the Cadence GenusTM integrated solution and InnovusTM. Design and implementation system, the test chip adopts industry-standard 64-bit CPU design, built-in custom 3nm standard cell library. The minimum metal winding pitch of the chip is only 21nm. 21nm this number may not be intuitive, if the benchmark single exposure If the 193nm lithography layout pitch does not exceed 80nm, then how advanced this design scheme is can be seen. Similar to the earlier 5nm test chip, the 3nm chip used EUV and 193i multiple exposure double hypotheses when studying the PPA target. The solution. To implement component interconnections, variables and resistors (especially contacts/vias) are the biggest challenges. For details, please refer to an IEDM short course I posted a few months ago: After 5nm One of the goals of the test chip is to measure and improve the variables. EUV technology for 3nm chips requires double exposure because the EUV 'light' has a wavelength of 13.5nm. EUV can also be used to test new pathways, as well as new materials such as cobalt and antimony.
Collaborative optimization of design technologies
In the past few decades, the expansion of process technology and the richness of design rules to the content library have been the driving factors for the development of Moore's Law; however, nowadays, it is not enough to rely on process expansion alone. The size of the standard cell library must be greatly reduced. The number of channels must also be reduced. To achieve this goal, we need to add additional process features that do not require direct expansion, such as active gate contact. In particular, we can add super vias on the MEOL to achieve optimization. Super vias are through holes that span more than one layer, occupy a minimum area, and do not require metal structures in the middle layer.
The biggest advantage of active on-gate contact (COAG) is that there is no need to place a separate gate contact outside the gate. Intel announced at the IEDM in December that its 10nm process (equivalent to what the fab claims The 7nm process) uses active gate contacts. I expect that the 5nm and 3nm processes will fully utilize active gate contacts, and some second-generation 7nm processes may use this technology.
In addition to the interaction between the process and the unit design, layout and routing are also very important. For example, under certain conditions, although free cabling channels will increase the cell area, the use of free cabling channels between cells can reduce the cabling area. The improvement of the wiring efficiency can completely offset the increase in cell area brought by the idle wiring channel.