Forward Error Correction (FEC) codes are used for control channels in high-performance 5G systems. AccelerComm's polarizing code solutions are based on a unique storage architecture that delivers the right information at the right time. Send to the correct processing unit to improve hardware efficiency, power efficiency and latency. With this IP for Achronix Speedcore eFPGA array architecture, lower power consumption and more than other optional, software-based methods can be achieved High Throughput. Instantiation of Polarized Code IP in Application Specific Integrated Circuits (ASICs) or System-on-Chip (SoC) equipped with eFPGA enables integrated solutions with minimal communication latency and lowest power consumption.
'We are very pleased to partner with AccelerComm to further enrich Achronix's partner program,' said Mike Fitton, Achronix's senior director of product planning and business development. 'Instantiating instantiation of AccelerComm's industry-leading polarization code in our eFPGA, Can support the ASIC and SoC equipped with Speedcore eFPGA to support the new standard by updating. We see that the ability to flexibly reprogram new requirements and emerging standards, will become the basic conditions for cost-effective deployment of 5G.
Achronix and AccelerComm will continue to develop solutions for future 5G versions. 'The 5G standard requires innovative development activities, especially the need to develop new features needed for ultra-reliable, low-latency communications and large-scale machine-based communications.' Chairman AccelerComm Acting CEO Tom Cronk commented. 'These new elements in the 5G Release 16 specification require innovation for emerging waveforms and new coding. AccelerComm's outstanding performance in IP engineering coupled with Achronix's flexible hardware acceleration portfolio, Can provide customers with a powerful means to support the ever-done communication infrastructure deployment.