At this stage, TSMC has a 100% market share in the 7-nanometer market. Many customers will begin mass production in June. Among them, Xilinx is the first to disclose the schedule, and its Everest product is the first to use TSMC's 7-nm process technology. The new ACAP product acceleration platform is expected to be put into production later, and will begin shipping in 2019. It's worth noting that TSMC's 7nm process is about to output, compared with Samsung Electronics' delayed line 18 plant. Groundbreaking, 7-nm manufacturing process will be the fastest production in mid-2019. Although the release of Qualcomm 5G chips has recently been won, the gap between TSMC process technology and TSMC's process technology continues to expand. TSMC process technology has led the opponent group significantly, following the 2017 10-nm process alone Taking Apple A11 processor orders, pushing up profits to write new highs, the slowest production rate of 7-nanometer process in June 2018 is 100% in the next year, and 85-90% in two years. In addition to taking orders for the Apple A12 processor again, Dahan also has a 10-nanometer switch from Samsung to Qualcomm, which has decided to return to TSMC. The latest X24 data processor chip and the Snapdragon 855 processor that debuted at the end of the year all place a single TSMC product. TSMC currently has at least 10 7-nanometer chips to finalize the design, and there will be more than 50 before the end of the year. In addition to Apple, Qualcomm, Hass, AMD, NVIDIA, Xilinx and other 7-nanometer process products will be available in the second half of the year. One of the most recent concerns is Bit Continental, whose demand for mining-specific chips (ASICs) has soared. In the second half of 2017, TSMC has become the main customer for production capacities of 16, and 12 nanometers. Sprint AI chip battlefield, the market is also expected to have the opportunity to use TSMC 7nm process technology in 2019. Xilinx unveiled the latest progress of 7-nanometer process products, officially announced the latest ultra-high integration of multi-core heterogeneous computing on the 19th The platform, Adaptive Computing Acceleration Platform (ACAP), code-named Everest, is the first ACAP product family to adopt TSMC's 7-nm process technology. It is expected to be put into production later, and will be shipped in 2019. After four years of research and development, it will accumulate research and development expenses. More than 1 billion US dollars, there are currently more than 1,500 hardware and software engineers responsible for the design, and related software tools have been provided to customers. In late January 2018 the official appointment of Xilinx CEO Victor Peng Said that the new ACAP series architecture will help Xilinx develop beyond the FPGA and break through the limitations of 'only supporting hardware developers'. In the era of big data and AI, ACAP is suitable for accelerating a wide range of applications including Video transcoding, database, AI inference, machine vision, computing storage and network acceleration, etc. Software and hardware developers can develop applications based on ACAP in applications such as endpoints, edge, and cloud. Victor Peng further pointed out that ACAP's new series will Taking data center as a priority, and accelerating the growth of the core vertical market and driving flexible response calculations, the new workload is 0 to 100 times faster than the CPU, and has a richer usage paradigm than the GPU and ASIC. Everest is performing Deep neural network computing is expected to increase performance by up to 20 times. Everest-based 5G remote radio head-end equipment will provide 4 times more bandwidth than current 16-nanometer radios; Automotive, Industrial, Scientific, medical, aerospace, defense and consumer electronics markets, etc., will all achieve significant performance gains and higher power efficiency. There is a whole core within ACAP. New generation FPGA architecture that combines decentralized memory and hardware programmable DSP blocks, a multi-core SoC, and one or more software programmable ACAPs also have chip control blocks for safety and power management, hardware programmable Memory controller that supports cache coexistence interconnect interconnect architecture accelerator (CCIX) and PCIe interface multi-mode Ethernet controllers, programmable I/O interface and sequencer, and some components also have high-frequency wide memory or programmable ADCs and DACs. Software developers can also use FPGA tools to program from the RTL layer.
