In the past ten years, open source software has become the biggest catalyst in the technology world. Now the power of open source has brought about free development, and the generated community has also gained a foothold in the hardware world. It is for these reasons that RISC-V has won Very high popularity. The following will introduce RISC-V and the opportunities it brings, and how CEVA helps chip makers to take full advantage of them.
What is RISC-V?
RISC-V is an open instruction set architecture (ISA) originally developed by the Department of Computer Science at the University of California, Berkeley. It is based on the popular Reduced Instruction Set (RISC), as well as ARM, MIPS, and other common commercial processor architectures. .
Since RISC-V began in 2010, it has now grown into a huge global cooperation project spanning multiple universities and industry sectors. Its consistency is made by the non-profit RISC-V Foundation (https://riscv.org /) Guaranteed, not only guiding the ISA specification, but also playing the role of a marketing engine to promote RISC-V.
It needs to be clarified that the RISC-V instruction set architecture, just as its name is, is an instruction set architecture specification, not a specific processor design. Starting from the open source instruction set architecture, many academic and industry teams have created many A differently designed processor, but essentially all the same language. A quick look at the RISC-V Foundation website, which shows a large number of processor implementations, from a complete open source processor design, such as Rocket, Orca and PULPino , To companies that produce commercial processor cores, such as SiFive, Codasip, Andes, and Cortus.
These processors have a wide range of implementations, from simple IoT processors to application processors running Linux, all based on a common set of instructions, reflecting the fact that RISC-V is a closed commercial ISA. The key advantages, namely differentiation and freedom of choice, can replace processor vendors without the pain of product refactoring.
Free, so there must be a risk, right?
In this regard, it is prudent to look at the actual situation and look at the factors that affect processor selection in new product designs. As with most design decisions, many technical and commercial factors are involved, some are based on rigid indicators, and some are based on difficulties. Quantitative aspects.
The technical indicators are self-evident: Including the processor has enough horsepower to support the scalability of subsequent products, whether it matches the envelope power, whether it meets the required security level, and whether there is a friendly and familiar software development/debugging environment, Can the user inherit the previous code base. Commercially consider the cost, such as area (including gates and memory size), royalties, and the entire license fee. It must also consider other business factors, including vendor lock-in, guarantees, and Compensation, business reporting obligations, legal rights to make changes, etc.
Considering all of these factors, most designs tend to adopt a 'safe' option, usually using a proprietary commercial processor, and are often tied to a previously used series. However, at the strategic level, many companies are increasingly restricting choices. Enhanced but powerful commercial processor IP vendors are uneasy. People are eager for more commercial freedom, breaking the lockout of closed instruction sets, which is not only meaningful in terms of licensing and copyright royalties, but also conducive to differentiation.
This demand makes RISC-V set sail. RISC-V's open source instruction set architecture provides chip companies with a realistic alternative to common business options and avoids overly strategic risks like linux, FreeRTOS and many other open source RTOS. The arguably alternative to commercial operating systems is today. Especially on small embedded processors used in consumer IoT devices, this choice is very realistic. Many well-known top companies, including Western Digital and Nvidia, have publicly announced With his own intentions, even large-scale production has already been carried out. More companies are evaluating RISC-V, some of which secretly started advanced designs.
CEVA's experience with RISC-V
Like these companies, CEVA has been attracted by the potential of RISC-V, especially our RivieraWaves Wi-Fi and Bluetooth IP products. These communication technologies require a small processor to execute the protocol stack, and our goal is to create a pre-integrated The reference platform allows our customers to freely select processors. Since the architecture of IP is designed to meet ultra-low power operation, even the advanced wireless network configuration, the demand for processor horsepower is also very mild. In brief, we need logic. With few gates, high energy-efficiency ratios, processor maturity, and a familiar commercial software development environment, it is possible to generate compact, space-saving code. The processor design must be easy to deploy (full speed operation) on FPGAs and ASICs/ASSPs, it must There is a legal framework that is compatible with our authorized IP services.
We chose the RISC-V processor core at the 20K gate level, which can achieve a good performance of 2.44 Coremark / MHz, which is exactly in line with the hardware requirements. Our internal performance and code-intensive test results show that we have achieved first-class shoulder-to-shoulder performance. Processor level. It is also important that based on our experience, the workload required to port a complete system to RISC-V is very small. Take the more complex Wifi platform as an example, replace with an embedded RISC-V processor Commercial processor, we took only one week to complete the integration, simulation and create a new FPGA binaries, to implement RivieraWaves complete Wi-Fi demo platform. In addition, the existing protocol software has been processed in a number of different commercial Developed and deployed on the device, it took only two weeks to migrate to the RISC-V platform, including porting, testing and system-level verification. This is not surprising, thanks to the familiar GNU GCC/GDB debugger and LLVM compilation / Environment.
Overall, this project was a great success. RISC-V truly fulfilled its commitment. CEVA is now a new member of RISC-V Foundation and is pleased to be able to provide RISC-V infrastructure as a platform to carry our Wi-Fi and Bluetooth IP core one option.