1. Samsung 7nm fab ground on Friday, 5.6 billion investment;
Set micro-grid news, Samsung Electronics in Hwaseong, South Korea's wafer fab this Friday (February 23) will officially debut, is scheduled for the second half of next year, mass production of 7nm chips, the future is expected to smart Devices, robots customized chips made good progress.
Pulse by Maeil Business News Korea reported on the 20th that Samsung plans to invest 6 trillion won (equivalent to 5.6 billion U.S. dollars) in upgrading its wafer capacity. The new wafer fab in Hwaseong City will install more than 10 extreme ultraviolet (EUV) lithography Equipment, as each EUV equipment as much as 150 billion won asking price, so the cost of purchasing the machine alone, it will reach 3-4 trillion won. Samsung Samsung 6nm fab construction plans, will be announced in the near future.
In contrast, TSMC has begun trial production of 7nm chip this year, is scheduled for the second quarter for the launch of MediaTek chip prototype, and early next year full production.
TSMC 5nm advanced process of 12-inch wafer fab January 26 this year, officially launched the first phase of the plant is expected to be completed in the first quarter of next year installed capacity, mass production into early 2020. TSMC announced until 2022 the first, The second and third phases of the plant are all in mass production, the annual production capacity is estimated to exceed one million twelve-inch wafer.
TSMC 2016 with superior front-end silicon wafer manufacturing and the latest packaging technology, Apple's application processor orders from the bowl away, Samsung determined to be ashamed, came out in 2018 to develop a new packaging process, buy back Apple orders.
South Korea's media ETNews reported on December 28, 2017 that the industry confirmed that the Samsung Semiconductor Group has invested in the proposed new Fan-Out Wafer Level Packaging (FOWLP) Oh Kyung-seok, director of the semiconductor research institute that hired Intel late last year, is in full production and Samsung firmly believes Apple orders can be successfully recaptured after the packaging process is completed, so the company will also build production equipment by the end of 2019 complete.
TSMC is the world's first foundry operator to commercialize the FOWLP technology for application processors and has won orders for the 16nm A10 processor for the iPhone 7 and the 10nm A11 processor for the iPhone 8. According to experts, Samsung, TSMC front-end silicon process technology comparable, but Apple's TSMC packaging technology evaluation is very high, but also decided to order to TSMC.
Insiders pointed out that Samsung has so far focused on the front-end process, not much investment in the back end, the loss of Apple's orders, Samsung finally feel the importance of back-end packaging.
2. The latest image sensor technology in ISSCC vying;
New Developments in ISSCC's Image Sensor Technology in 2018 Beyond the previous focus on "beauty pageant" image capture, adding more contextual information ...
At the International Solid-State Circuits Conference (ISSCC) in 2018, there are several new developments in image sensor technology that go beyond image capture that previously focused on "beauty pageant" to add more contextual information; these new developments include An event-driven sensor, a new global shutters method that solves the problem of image distortion in motion, and a time-of-flight (ToF) image sensor.
CMOS image sensor with motion detection
Sony's event-oriented, low-power CMOS sensor at ISSCC is a good example of adding situational information to captured images. The company's team of design engineers deployed motion detection directly inside the image sensor )Features.
In a paper, Sony details a quarter-inch, 3.9-megapixel low-power event-oriented back-illuminated stacked CMOS image sensor that incorporates a pixel read circuit (pixel readout circuit) that detects every pixel of a moving object.According to the description of the Sony development team, the behind-the-scenes motivation for developing this event-oriented image sensor is to meet those low-power, never-off devices, Image quality imaging needs.
With the rise of wireless networking devices such as home security cameras and virtual personal assistants, system-on-a-chip (IoT) system designers are also looking for small solutions that extend battery life, and event-oriented technologies are well suited for securing system applications; such image sensors Built-in intelligence, real-time detection of moving objects.
Sony's event-oriented sensors include pixel arrays, row drivers, row decoders, single-slope generation, motion / light detection blocks, video signal processors, Frame memory SRAM, MIPI ports, and CPUs linked to the sensor control block
(Source: Sony)
As shown above, when the Sony event-oriented sensor detects a moving object, the CPU generates an external interrupt signal that uses zero-delay to trigger the capture of high-quality video using on-chip auto exposure. Sony said the video The sensor utilizes the pixel summation of the floating diffusion shared by each pixel block to achieve a moving object detection of 10 frames per second.
Abhinav Mathur, a senior embedded software engineer at Sony's Image Sensor Design Center in Silicon Valley, said that the image sensor operates at just 1.1mW while consuming 95mW at the same full resolution at 60 frame rate CMOS image sensor, In event logging applications, this sensor significantly reduces power consumption and data bandwidth in the camera system's low-power sensing mode.
Sony event-oriented sensor function block
(Source: Sony)
ToF Sensor Technology Progress
The focus of the technology is on higher resolution, lower power consumption and smaller size; Microsoft (ISSCC) at the ISSCC presented a brief overview of ToF sensors for use with the Kinect 2 motion sensing device, Is an improved Continuous-Wave (CW) ToF technology that claims to push the latest ToF sensor to megapixel.
Microsoft's latest ToF sensor
(Source: Microsoft)
Microsoft's team believes that the CW ToF imaging system offers excellent mechanical strength, no baseline requirements, and high-performance deep image resolution, low computational cost, and IR ambient light intensity in a variety of 3D image capture technologies available on the market The team is committed to improving the spatial resolution, accuracy, and operating range of CW ToF cameras while reducing their work-focus (ie, the ability to synchronize the IR ambient light invariant intensity) - the active brightness - Consumption
In addition, Microsoft also improves the uncertainty and power consumption of CW ToF image sensors by increasing modulation contrast, quantum efficiency, and modulation frequency, eliminating read noise and analog-to-digital conversion while reducing it with smaller pixels The height of the optical stack.
Microsoft's ToF sensor specification
(Source: Microsoft)
The small form factor (3.5 x 3.5μm) is crucial for the next generation of ToF sensors to compete in smart phone applications, which Microsoft claims are competitive with commercial global shutter RGB sensors and small optical stacks for handheld devices; The 1024x1024 pixel ToF global shutter image sensor described in the ISSCC paper achieves a modulation contrast of 87% at 200MHz with 65nm 1P8M back-end CMOS technology from TSMC.
Pixels within the noise elimination
Panasonic at ISSCC showcases recent advances in its organic photoconductive film (CMOS) CMOS image sensor technology - Separating the optoelectronic conversion capability from circuitry in the OPF CMOS image sensor; with this unique architecture, the company's team The newly developed high-speed noise cancellation technology and high saturation technology into the circuit, while using the sensor's unique sensitivity control to change the voltage applied to the OPF, thus achieving the global shutter function.
OPF CMOS image sensor compared with the traditional global shutter sensor architecture; Panasonic claims its latest sensor is the industry's first to provide 8K resolution, frame rate of 60fps, 450k electronic saturation, and have the global shutter function
(Source: Panasonic)
In the past, high-resolution, high-fidelity cameras for broadcast, television and security applications, such as the 8K ultra-high definition television system and the 8K camera with a stack sensor scheme, had the common flaw of rolling-shutter rather than global Shutter. In global mode, the shutter operation simultaneously captures images of all pixels, while the Rolling Shutter mode CMOS image sensor exposes and operates in a row by row manner.
Panasonic said the rolling shutter will cause distortion problems, especially in high-speed imaging and multi-view image synthesis applications
(Source: Panasonic)
Panasonic's newly developed sensor, claimed to capture undistorted moving body images in real time, is of particular interest to multi-view and high-speed, high-resolution cameras such as machine vision and intelligent traffic monitoring systems; and because photoelectric conversion and The circuit can be designed separately, using the in-pixel gain-switching technique to achieve high saturation characteristics, and voltage-controlled sensitivity modulation techniques to adjust the sensitivity by changing the voltage applied to the OPF.
Panasonic newly developed CMOS image sensor can capture 8K resolution images, and even in high-contrast scenes, with global shutter function, full pixel capture synchronization images
(Source: EE Times)
Supports up to 200 meters of imaging light
Toshiba's team of engineers at ISSCC published the latest technology in long-range, high-resolution LiDAR systems that make use of ToF information from reflected photons; and because the goal is distance measurement distance measurement, DM), the team will support the ideal distance of 200 meters, the car traveling on the highway, sensing the approaching other vehicles or objects.
The Toshiba team also pointed out that to achieve safe and reliable autonomous vehicles in urban areas, the light system must have a wide range of perspectives and high resolution in order to complete perception of the surrounding situation; to achieve this goal, a thorny challenge is that the light Often, the system confronts strong background lighting such as sunlight, which is also the main source of noise for the light system.
Vehicle detection of light system up to the requirements and Toshiba's solution specifications
(Source: Toshiba)
Toshiba introduced a Kawasaki SoC that combines a Time-to-Digital Converter (TDC) with an analog-to-digital converter (ADC) and has a Smart Accumulation Technique (SAT) ) Function, claiming to allow the light system to reach 200 meters of line-of-sight and high-resolution images for autonomous vehicles.
According to Toshiba, the SAT can take advantage of the intensity and background information from the ADC to identify and accumulate data that is reflected only from the target, thus achieving four times the resolution of a traditional accumulation technique. The TDC / ADC combination The architecture relaxes the need for ADC sampling rates to support short-range DM accuracy; in addition the proof of concept supports a 200-meter-distance light system with DM distances up to twice the traditional design for 240x96 pixel resolution with 0.125% DM Accuracy.
Performance Comparison of Toshiba Light Solutions with Traditional Design
(Source: Toshiba)
Pixel parallel bonding technology
Not only Panasonic, Sony also noticed the problem of image distortion of moving objects captured by rolling shutter image sensors, pointing out that in-pixel analog memory and pixel-parallel ADC are potential solutions. However, these technologies Can not support megapixel resolution because neither of them addresses the timing constraints of reading and writing ADC digital signals in one pixel.
Sony's proposal in the ISSCC paper is to use a stacked image sensor with a single ADC per pixel to implement a global shutter in a CMOS sensor
(Source: Sony)
Sony's stacked back-illuminated CMOS image sensor with a 1.46-megapixel 14-bit ADC in pixel-level bonding technology said the company has a subthreshold comparator with forward feedback circuitry, Helps to minimize the comparator current and circuit area, and reduces power consumption.
Compile: Judith Cheng
(Reference text: Rivals Expand Image Sensor Scope, by Junko Yoshida) eettaiwan
3.5 large indications memory chip "super loop" will end;
Finance column "Seeking Alpha" columnist pointed out that Apple cut iPhoneX production, as well as the mainland semiconductor company is expected to be completed in 2019 by the memory factory settings, supply and demand changes in memory, the expected increase in production capacity, the global DRAM average The price will be lower.
Robert Castellano, Seeking Alpha columnist, said there are five signs that the "hypercycle" of memory is coming to an end.
1. The average memory selling price is falling
Based on the data provided by Korea Investment & Securities, the authors reconcile the average ASPs of NAND and DRAM between 2016 and 2018. The data show that the average selling price of NAND and DRAM of Samsung Electronics SK hynix has been declining in recent quarters .
Samsung NAND and DRAM average sales price changes
SK Hynix NAND and DRAM average selling price changes
2. Mainland Development and Reform Commission and Samsung sign a memorandum
Mainland China's National Development and Reform Commission and Samsung Electronics signed a memorandum on chip cooperation that will potentially cooperate in the field of chip manufacturing, artificial intelligence and semiconductor manufacturing. Industry analysts said the cooperation between the two sides will probably cut DRAM prices and increase output in the global DRAM market.
3. Samsung NAND flash memory expansion capacity reduction
Samsung decided to boost memory capacity in 2018 to limit rival profit growth and increase barriers to entry for potential Chinese competitors Samsung had previously expected to open new floors at its Pyeongtaek, South Korea facility to create a new NAND Flash memory production line, but after the price drop, Samsung plans to set up DRAM production lines in some areas on the second floor instead.
DRAMexchange expects DRAM supply to grow by 22.5% in 2018, up from approximately 19.5% in 2017. DRAM revenue is expected to grow 30% in 2018, well below the 76% revenue growth in 2017.
4. Mainland manufacturers to complete memory factory settings
The memory factories of mainland semiconductor manufacturers may start operation as early as the end of 2019. Jinhua IC Company in Fujian pointed out that the construction progress is expected to be completed and the construction of major factories is expected to be completed in October this year. The headquarters of the company is located in Wuhan Of the Yangtze River storage technology companies will invest 2.4 billion US dollars to build three large-scale 3D NAND flash memory manufacturing plant, the first plant is expected to be officially started production in 2018, the monthly capacity of about 300,000 wafers, and finally, in Hefei Core force integration Circuit company, bought a number of DRAM production equipment.
In addition, Apple (AAPL-US) is approaching the storage technology company in Yangtze River, will likely buy memory chips from them, the current suppliers of Apple's NAND flash memory for Toshiba, Witten, Samsung and SK hynix.
Apple iPhone X production under half repair
Sean Yang, an analyst with Shanghai research firm CINNO, said that Apple, the largest consumer of these chips, accounted for about 1.6% of global total demand in 2017 at about 160 million gigabytes. The reduction of consumers with memory chips will slow NAND and DRAM and average selling price increase.
Ju Heng network
4. Fourth quarter 2017 server DRAM revenue growth of about 13.9%;
According to a DRAMeXchange survey, in the fourth quarter of 2017, the demand for North American data centers continued to be strong. Even though the original product line was adjusted, it still can not effectively relieve the market The tight supply situation in Server DRAM benefited from the average Selling Price, which rose 13.9% quarter-on-quarter for the three DRAM makers.
Liu Jiahao, a senior analyst at DRAMeXchange, pointed out that in the first quarter of 2018, despite the unabated server shipping, the overall market demand for Server DRAM is still in short supply while the quotation of Server DRAM modules will remain at a high level.
Samsung
Benefiting from the data center construction and the demand for high-capacity modules, the fourth quarter of 2017 Samsung Server DRAM revenue performance is particularly dazzling, not only the bit shipments increased by 8% in the third quarter, the average retail price also Up from the previous quarter, revenue rose 14.5% from the third quarter to 2.92 billion USD, accounting for about 46.2% of the overall market. Samsung will still continue to adjust the supply compliance rate for each OEM / ODM at this stage in the hope of meeting the major customers The demand then increases the profitability.
SK Hynix
Due to the demand from North American data centers, SK hynix is more active in configuring Server DRAM products, accounting for more than 30% of total Server DRAM output in the fourth quarter.Secondly, the demand for high-capacity modules driven by new platform conversions , But also for SK hynix Q4 revenue growth of 10.9% more than the third quarter to 1,988,000,000 US dollars, operating profit margin improved over the third quarter of 2018 due to server memory demand will remain high, SK hynix will Will increase the proportion of Server DRAM output quarter by quarter, and focus on the new process of 18nm products into the penetration and penetration.
Micron
In addition to the sustained price increases and the cost-effectiveness brought by the miniaturization of the process, in addition to the fourth quarter of Server DRAM bit-bit shipments growth over the previous quarter, the average selling price has also jumped significantly, its Server DRAM revenue growth of 17.2% Reaching 14.14 billion US dollars, the city accounted for 22.4% of the level.On the product side, Micron's proportion in Server DRAM remained at nearly 30% of the water level, the continued growth of profits at this stage entirely depends on the memory average sales price increase.
5.Windows 10 on ARM can not run a specific OpenGL version of the game;
Set micro-messenger news, Microsoft last year released the ARM architecture processor Windows 10 networking devices, more details recently released, not only does not support x86 programs, nor can the implementation of a specific OpenGL version of the game
Microsoft announced at the end of 2016 that it will work with Qualcomm to build Windows-based devices using ARM processors and released the first Windows 10 laptops with ARM processors late last year, claiming that in addition to its high performance, low power consumption, Connected PC, it is also compatible with x86 Win32 and Universal Windows programs, though Windows 10 on ARM still has a few limitations compared to Windows on x86.
Microsoft last week inadvertently disclosed the Windows 10 on ARM program and experience restrictions, although Microsoft will soon delete the file, but it has been Internet Archive save.
From a restricted list, Windows 10 on ARM supports only ARM64 drivers, x64 programs, games or programs that use a particular OpenGL version, some customizations that do not work well, and some programs that work on mobile Windows There are layout problems, nor does it support Hyper-V.
The above limitation means that peripheral manufacturers must recompile x86 drivers into ARM64 versions and Windows 10 on ARM only supports programs that use DirectX 9, DirectX 10, DirectX 11, and DirectX 12, and do not support OpenGL version 1.1 or later Hardware accelerated OpenGL games or programs.
Looks like Windows 10 on ARM is still suitable for most scenarios and programs, Microsoft also provides solutions for certain restrictions, the outside world is that until after the actual machine to enter the market to confirm the ability of related equipment. The first to be listed this spring Both Windows 10 on ARM notebooks will be ASUS NovaGo and HP's Envy x2can, all boast up to 20 hours of battery life.
6.MIT develops new AI chips to bring neural networks to mobile devices
Researchers at the Massachusetts Institute of Technology (MIT) have developed a new type of artificial intelligence (AI) chip that boosts neural network operations three to seven times faster while reducing power consumption up to 95%.
According to TechCrunch and Tech Xplore, the chip was developed by a team led by MIT graduate student Avishek Biswas and its greatest strength is its ability to run neural networks on smartphones, home appliances, and other portable devices rather than on high-power servers road.
This means that in the future handsets using the chip can use neural networks for speech and face recognition and native depth learning instead of using a more coarse, rule-based algorithm or sending information to the cloud for analysis and returning results.
Biswas said that in general AI chip designs have a memory and a processor that will move data back and forth between the memory and the processor.Machinery algorithms require a lot of computation so the data is transmitted back and forth most efficiently, The operation of these algorithms can be simplified to a specific operation called a dot product, which eliminates the need to transfer data back and forth if the dot product operation can be performed directly in the memory.
Neural networks are usually divided into many layers. A single processing node in a network layer usually receives data from several nodes in the lower layer and passes the data to multiple nodes in the upper layer. Each connection between nodes Has its weight.And the process of training neural network is mainly to adjust these weights.
When a node obtains the data of multiple nodes in the lower layer, it multiplies each data by its weight and adds these results. This process is called dot product. If the dot product exceeds a certain threshold, the result will be Is sent to the upper node.
In fact, these nodes are only the weights stored in the computer's memory.Calculating the dot product usually involves reading the weight from the memory, getting the relevant data, multiplying the two, and storing the result somewhere and at the node's This is repeated for all input data, and given that there will be thousands or even millions of nodes in a neural network, large amounts of data must be moved in the process.
But this series of operations is to digitize the events in the brain where signals travel along multiple neurons and meet at the synapse.And the firing rate of neurons and the voltage across synapses Of the electrochemical signal corresponds to the data values and weights in the neural network.MIT researchers' new wafers increase neural network efficiency by more faithfully replicating brain activity.
In this chip, the node's input value is converted to voltage, multiplied by the appropriate weight. Only the combined voltage will be converted back to the data, and stored in memory for further processing. Therefore, the prototype chip can simultaneously calculate 16 Dot product of the nodes without having to move the data between the processor and the memory every time the operation is performed.
Dario Gil, vice president of IBM AI, said the results of the study are expected to open up the possibility of using more complex convolutional neural networks for image and video classification in the Internet of Things (IoT). DIGITIMES