The complexity of chip design and rising costs are hindering the entry of hardware startups into the market. It is estimated that the cost of a new chip may reach as high as $ 120 million, depending on the chip design, software and manufacturing process, not only unfavorable market competition but also According to The Next Platform, DARPA and Semiconductor Research Corporation, which provide $ 27.5 million in research funding to encourage start-ups and market competition, hope the design and manufacturing process And reduce the cost and complexity of developing advanced computing systems, one of which is led by the Center for Applications Driving Architectures, Professor Valeria Bertacco said the center will develop a satellite-based Bertacco said it hopes to see newly graduated college students start their own hardware company in just five years as long as they focus on the needs of a particular application's algorithm, May create a calculus hardware architecture or heavy Bertacco said that rather than targeting the application itself, the design will focus on the underlying algorithms, and each dedicated hardware design will be several orders of magnitude more efficient than a general-purpose chip, a purpose-built hardware design It has been around for a while now, but it can take as long as 10 years to see a mature and efficient solution that can raise the abstraction level above the deep-tech chip design issues such as timing and power optimization. From a hardware perspective The idea is to make computing a packaging issue rather than a problem that needs to be addressed from scratch. Newer semiconductor engineering and manufacturing developments, such as the 2.5D technology that uses silicon interposers to bond bare dies with different process / operating characteristics and packages them together, The idea is that in the future, chip companies will be able to produce off-the-shelf processor cores and accelerators, and anyone can buy an interposer to take advantage of the chip maker's economies of scale to design and save hundreds of thousands or even millions of dollars. Bertacco pointed out that for non-applicable FPGA and can not take full advantage of the special field of CPU efficiency, it applies The idea is to offload multiple accelerators to the algorithmic approach that adjusts the compiler, obscuring the boundaries between hardware and software, thinking at the application level, and considering how the compiler can automatically take advantage of accelerator-specific applications to achieve the desired performance. Bertacco said the future will be defined by heterogeneous multiplex processors, and existing accelerators defined by applications and compilers will also work.
