To address the 2018 and the most anticipated semiconductor process technologies for the next five years, in addition to the upcoming production of the 7nm FinFET tip process and the 5nm process node expected to fully introduce extreme ultraviolet (EUV) lithography, It is also a focus of industry that various foundry vendors are looking at a wide range of low to mid-tier process technology options for low-power, low-cost component needs in the widely-used, all-encompassing Internet of Things (IoT) market.
Such as the 16 and 12-nanometer FFC (FinFET Compact Technology) of wafer foundry TSMC, 22 nanometer ultra low power (ULP), 28 nanometer HPC / HPC +, and 40 nanometer ULP, 55 nanometer ULP with low power consumption (LP), Intel's 22nm low power FinFET (22FFL) process, GlobalFoundries' 28nm HPP (High Performance Plus) / SLP (Super Low Power), 22FDX process, and Samsung Electronics Samsung's 28nm FDSOI, LPP, LPH ... and more are solutions that address the needs of a wide range of IoT applications.
One of the biggest differences between GlobalFoundries' FDX series process and Samsung's FD-SOI process, among other competing solutions, is the use of Fully Depleted Silicon which is hard to read both in English and Chinese. Silicon On Insulator, FD-SOI) technology pioneered in the industry by SOI Industry Consortium, STMicroelectronics and its research and development partners IBM, GlobalFoundries, and Samsung in 2011, The 28nm and 20 (22nm) nano-nodes can achieve the equivalent performance of next-generation FinFET processes supported by Intel, TSMC, and others with lower cost and less risk.
FD-SOI technology advantages?
Unlike the 3D transistor structure used in the FinFET process, the FD-SOI is a planar process. According to ST's official technical literature on the net, FD-SOI has two major innovations: the first is the use of buried oxide (BOX) Thin insulating layer placed on the silicon substrate; then the thin silicon film is deployed in the transistor channel, because of its ultra-thin thickness, the channel does not need dope (doping), so that the transistor can be completely depleted in the above two The combination of all kinds of innovative technologies is called "ultra-thin body and buried oxide FD-SOI (UTBB-FD-SOI)".
ST said that FD-SOI provides better transistor ESD performance than conventional bulk silicon technology, while buried oxide reduces the parasitic capacitance between the source and drain; In addition, this technique effectively limits the flow of electrons between the source and the drain, drastically reducing the leakage current that affects the performance of the device (Figure 1). In addition to the gate, the FD-SOI can also polarize the underlying substrate To control the transistor behavior, similar to the bulk bias that bulk silicon technology can achieve.
However, the bulk bias of bulk silicon technology is very limited, because the parasitic leakage current and transistor geometry reduce the efficiency of the transistor decreases; and FD-SOI due to the crystal structure and ultra-thin insulating layer bias efficiency will be better. , Buried oxide can also achieve a higher substrate bias to achieve breakthrough dynamic control of the crystal ─ ─ when the substrate is the polarization of the forward, which is forward matrix bias (FBB), the transistor switching speed Can speed up, and thus optimize component performance and power consumption.
According to ST, FD-SOIs easily implement FBBs and dynamically adjust during transistor operation, providing design engineers with a high level of flexibility, especially with respect to power-saving performance and speed, where performance is not critical, The ideal solution for networking or portable / wearable consumer electronics applications.
In a 2014 report, Handel Jones, chief executive of international business strategies (IBS), a market research firm, wrote: "The same 100mm square chip, using a 28nm FD-SOI process costs 3 times less than a bulk CMOS process %, Which can be further reduced by 30% at the 20nm node. This is because the higher the yield of the parameters, the lower the wafer cost. In addition, the die complexity of the FD-SOI process is compared with that of the bulk CMOS process , Low 10% ~ 12%.
Jones further said: 'The combination of smaller die area and higher parametric yield yields 20% more product cost advantage over the 20nm node for the FD-SOI process and 20% for the bulk CMOS process. At the 28nm node, the FD- SOI delivers up to 15% better performance than 20nm bulk CMOS. "He also pointed out: 'The FD-SOI process offers higher energy efficiency levels for high / low Vdd than bulk CMOS processes, The power efficiency of FD-SOI over bit cells is also higher than bulk CMOS due to lower leakage currents and better immunity to alpha particles.
FD-SOI process: Western cold, hot East
However, FD-SOI is claimed to have many of the advantages described above, and the manufacturing yield, the cost of proprietary wafers, and the stability of the source of supply, as well as the exact time history of mass production, and the overall technical support for ecosystem integrity are still among the industry So many FD-SOI supporters in Europe, including ST, NXP (NXP) and other supporters, Samsung, GlobalFoundries also actively promote their own FD-SOI foundry business, the technology in the market's discussion of heat and visibility has been low Especially in the West.
As of February 2017, GlobalFoundries announced that it will invest USD 10 billion to set up a 12-inch fab in Chengdu Hi-tech West Zone (Figure 2). The first phase of production that will commence operation in 2018 will be a more mature transfer from its Singapore plant Of the 180/130 nm process and the second for the 22FDX FD-SOI process line from its Dresden facility in Germany, expected to begin operation in 2019; this message has aroused widespread repercussions in the semiconductor industry, except once again The mainland's ambition to develop the domestic semiconductor industry chain also represents that the "main battle line" of the FD-SOI process will be ignited on the mainland.
Mainland China expressed its great interest in FD-SOI technology as early as 2015 when Wayne Dai, chief executive of VeriSilicon, a provider of IC design services in mainland China, told EE Times reporters that instead of continuing to work on the FinFET process To follow up with TSMC or Intel, he believes the mainland should invest in FD-SOI and use this technology as an alternative to low-power processes. In addition, Shanghai's Simgui will start mass production of the first 8-inch SOI wafers, using Smart Cut process technology from Soitc, the company's strategic partner.
There is also an investment platform set up by a large fund, with the National Silicon Industry Group (NSIG) announcing its 14.5% stake in Soitec in 2016; the chip foundry Shanghai Huali Microelectronics Corp.) revealed plans for investing in FD-SOI production lines before GlobalFoundries announced its investment plan for the Chengdu plant, but no specific timetable is available, indicating that the FD-SOI will be part of the blueprint for the semiconductor industry in mainland China May make this so far in the Western world market slightly less skillful technology, shiny in the East market fever.
According to Alain Mutricy, senior vice president of product management at Globalfoundries, in an interview with the EE Times in May 2017, the company's investment in setting up factories in Chengdu is only the first step, followed by the establishment of an FD-SOI ecosystem in the mainland to help the mainland Foundry IC design firms and design service providers easier to obtain the required IP and tools.
IoT process war is about to explode
At the end of September 2017, Sanjay Jha, CEO of GlobalFoundries, who delivered the keynote speech at the 5th Shanghai FD-SOI Forum sponsored by the SOI Industry Alliance, once again vigorously promoted the FD-SOI process at 22 nanometers - using a single mask minimum Node is also suitable for cost / power sensitive applications such as Internet of Things, portable devices and the like, and is expected to be the 'longevity' node in the market ─ as a benchmark, the company's 22FDX process and the Intel 22FFL process, TSMC 22ULP process Performance comparison (Figure 3).
In an EE Times China interview after the keynote address, Jha said: 'From a cost point of view, the 22nm FinFET with planar technology will have more process steps and higher process control complexity. For FDX, the underlying substrate cost may Will be higher.It is very difficult to analogize the structure of their respective costs, but considering our cost of construction investment in the wafer fab in China and the scale of the cost effect, in terms of production costs, compared to Intel's technology may have a slight advantage '
In the same forum, Jones, IBS chief executive, further proposed a cost per-gate analysis of the FD-SOI process (Figure 4). He pointed out that the 28-nanometer FD-SOI process and the 28-nanometer high- Gate costs for very large (HKMG) bulk CMOS are quite comparable, and the gate cost for 22-nanometer FD-SOI is still competitive. In the next generation of 12-nanometer FD-SOI, which requires less photomask, Ultimate cost is 22.4% lower than the 16nm FinFET process, 23.4% lower than the 10nm FinFET and 27% lower than the 7nm FinFET, while the low power consumption of the FD-SOI is certainly better than the FinFET.
In addition, Jones also proposed hardware and software design process cost comparison (Figure 5) for each process node. The design cost of the 12-nanometer FD-SOI is estimated to be between $ 5,000 and $ 55 million, while the design cost of a 16-nanometer FinFET is around $ 72 million. The 10-nanometer FinFET design costs about $ 131 million; and because the design result requires 10 times the cost of revenue, the 12-nm FD-SOI will have a larger market size (TAM) than 16-nm and 10-nm FinFETs.
GlobalFoundries considers mobile devices, the Internet of Things (IoT), wireless communications (5G / LTE / Wi-Fi), and automotive (ADAS / automotive communications) as a combination of features and cost advantages such as low FD-SOI power consumption and ease of integration with RF Jones claims that 90% of existing 28-nm process components are suitable for FD-SOI processes, with an estimated TAM size of $ 17.1 billion in 2018 (Figure 6) and even up to 2025 18.4 billion U.S. dollars. How much revenue each vendor of FD-SOI technology can actually make depends on its capabilities. The battle for the warranties in the Internet of Things market has been soggy.
Mainland IC manufacturers eager to Taiwan manufacturers?
According to statistics provided by GlobalFoundries at the 5th Shanghai FD-SOI Forum, the company's 22FDX process has garnered a total of 135 customers, 20 of which will enter the multi-project wafer (MPW) test by the end of 2017 15 of them will be officially put into operation by the end of 2018. Among the customers entering the test design / project phase are 10 manufacturers from mainland China.
After GlobalFoundries announced the construction of a 12-inch new plant in Chengdu with a total investment of 10 billion U.S. dollars in February 2017, Global Foundry announced in May of the same year with the Chengdu Municipal Government that the two sides will work together to build a cumulative investment scale of over 100 million in 6 years The USD's 'world-class FD-SOI ecosystem' covers a number of R & D centers in Chengdu and research projects with universities and colleges that aim to attract more top semiconductor manufacturers to Chengdu and make Chengdu the next generation Chip design center of excellence '.
Companies that will join Chengdu's FD-SOI ecosystem include EDA vendors Cadence, Synopsys, design services vendor VeriSilicon and Invecas, as well as chip design houses MediaTek, RockChip, Shanghai Fudan Microelectronics Group Company) and others. In an interview with EE Times, Dai Weimin from VeriSilicon stated that to obtain R & D funding from Chengdu's FD-SOI ecosystem investment, "every company must deploy its research and development team in Chengdu."
Dai Weimin pointed out that FD-SOI backers have laid the groundwork for the mainland and continue to promote local chip makers and IC design engineers, government officials and private investment funds through events such as the Shanghai FD-SOI Forum. In his opinion, there are several key points to expand the FD-SOI ecosystem: the feasibility of using FD-SOI for mixed-signal and RF design, the support of design service providers such as VeriSilicon, the substrate bias design flow and Tools, design education, seminars, university courses, labs and textbooks, and government support.
GlobalFoundries said FD-SOI process ecosystem FDXcelerator partners have reached 33 as of September 2017 (Figure 7), while global IC manufacturers are desperate for FD-SOI technology and the local industrial ecosystem is gradually forming. , Covering the upstream and downstream manufacturers in the semiconductor industry chain. Although Taiwan occupies a very small number of manufacturers, including the packaging and testing giant ASE, embedded memory IP provider eMemory, and processor IP provider Anxin Technology (Andes).
In an interview with EE Times, Lin Zhiming, general manager of Crystal Heart Technologies, said in the interview that in 2015, the company cooperated with Global Foundries' longtime partner, US IC design service vendor Invecas, to import its 32-bit N7 processor core into the FD-SOI process reference Design, and later won GlobalFoundries' 22FDX process validation.
He pointed out that the heart of the processor core development was originally based on low power consumption, high efficiency as its N7, N8 and N9 series have been used in the Internet of Things and portable consumer electronics market, presence, including smart watches , Smart voice assistants, game consoles and portable karaoke microphones, etc. The target market is in the same direction as the FD-SOI technology. With this process option and the crystal IP, it is expected to bring better power saving to customers' designs efficacy.
Taiwan's semiconductor IP suppliers are not absent in the FD-SOI ecosystem, but when will Taiwanese IC design companies follow up? In addition to MediaTek, which is already preparing to join Chengdu's FD-SOI ecosystem, local Taiwanese companies' attitudes toward the technology As cold as the Western market; such as semiconductor test laboratory iST (iST) said that it is understood that Taiwan is trying to FD-SOI design IC manufacturers are still a minority, the process is expected to accept much slower than the mainland manufacturers .
Conclusion
Huang Zhiyu, an analyst at Semiconductor Research Center of Taiwan's TrendForce Research Institute, said that at present, statistics of global FD-SOI production capacity are not easy to obtain and can only roughly estimate that the process occupies the global wafer generation in 2017 The proportion of workers sold was about 0.2%. He also pointed out that mainland China has actively established the FD-SOI industry chain and introduced wafer fab maker Soitec and wafer foundry GlobalFoundries to compete with Taiwan foundries' 28-nanometer process competitiveness May bring impact.
However, Huang pointed out that it is also important to observe the timing of FD-SOI production capacity in mainland China. We must also consider the depreciation of the 28-nanometer process and the actual capacity of the FD-SOI in the market for existing foundries: FD-SOI process capacity of small scale, the cost is relatively high, and if foundry depreciation in good condition, will be able to provide a more favorable price of 28-nanometer process, so in the cost-oriented end-product competition, FD-SOI It may not be beneficial.
28nm process can be said that Taiwan's foundry Hutch Union UMC (UMC), TSMC's 'cash cow', including TSMC in 2017 28-nanometer wafer shipments hit a record high of 180,000, the node camp In the third quarter of 2017, TSMC still occupied the highest quarterly overall revenue, reaching 27%, higher than the advanced 16 / 20nm node. In the third quarter, UMC saw a slowdown in market demand for 28nm HKMG.
What will the impact of the menacing FD-SOI process have on the existing 28-nanometer foundry market? Will the mainland semiconductor industry rewrite history due to the development of FD-SOI technology? TSMC's forthcoming 22nm new Process and whether it can get the market power? For the networking market opportunities, UMC in the 28-nanometer process will sacrifice what new 'weapons'? 2018 semiconductor market development situation worth one after another observation!