Solid-state hard disk (SSD) penetration and adoption rates have increased significantly, both in the enterprise and consumer markets. The benefits of SSDs over traditional hard drives include several times the transmission speed, as well as greater capacity with low power consumption and low noise In recent years, the cost per unit of storage for solid state drives has continued to drop, bringing the price gap with traditional hard disks getting closer and closer to each other. This market has moved toward the gradual replacement of traditional hard disks.
The market demand for SSDs is trending toward higher performance, higher capacity and lower cost. NAND Flash, the main component of SSDs, also needs this kind of product features in response to such market demand.
With the market demand, in order to further improve the solid state drive capacity and reduce cost per bit, the traditional 2D NAND Flash process continues to scale down, and the number of transistors needed per unit area of an IC is constantly increasing.
As Gordon E. Moore, one of Intel's founders, put forward the so-called Moore's Law in 1965 - the number of transistors in a single silicon chip will double every eighteen to twenty-four months.
Traditional 2D NAND Flash is facing manufacturing challenges
The 2D NAND Flash structure mainly adds a layer of floating gate made of polysilicon into the transistor. The floating gate is mainly used as a storage charge, and the amount of stored charge can be used to judge whether each memory cell (Cell) The storage status is 1 or 0 (Figure 1).
Due to the miniaturization of the process, the distance between the floating gates of each memory cell is getting closer and closer. When the distance is less than 20 nm, the problem of Cell-to-Cell coupling coupling becomes more and more serious (Figure 2). Coupling interference can cause memory Storage unit storage status error, resulting in storage data error.
Figure 2 process derivative derived Cell-to-Cell coupling.
Process shrinkage has some physical limits, and the process continues to shrink, due to technical difficulties, but also gradually increase costs. However, the consumer market is still in need of higher capacity, lower cost solutions. In view of this, each Memory manufacturers began to actively develop 3D NAND Flash.
3D NAND Flash technology mainly by the stack more layers to replace the 2D NAND Flash process miniaturization.That no longer by process miniaturization technology, but by vertically stacking the storage unit to increase capacity, to solve because the memory storage The floating gate close between the cells, leading to the problem of increasingly serious coupling interference; at the same time to achieve higher product capacity, lower cost market demand.
Although the 3D NAND Flash product features can meet the current market needs, but there are still problems inherent in the process, and need to match the NAND Flash controller has a higher error correction capability.
The structure of the 3D NAND Flash is composed of a stack of polysilicon, oxide, nitride, oxide and silicon, which may be referred to as SONOS.
Due to the physical characteristics of SONOS, the chance of charge loss is greater than that of a traditional floating gate, and the Read M argin is smaller than the MLC, so the probability of 3D TLC Flash data errors Higher, so with the 3D TLC Flash, NAND Flash controller needs to have a higher error correction capability.
To this end, NAND Flash suppliers have developed three-stage high-efficiency error protection protection mechanism, including LDPC (Low-Density Parity-Check) Hardbit Decode, LDPC Softbit Decode, SmartECC Engine, can effectively extend the life of 3D TLC NAND, enhanced solid state drive Product reliability.
To 4K LDPC error correction first check
In the error protection stage of LDPC, error correction is performed in units of 4K Byte. When a Page Program is performed on a NAND Flash, a corresponding write is made in a Spare Area The check data code is generated by a generator matrix code, which is generated every 4K bytes of data.
When reading NAND Flash data, the Parity Check Matrix is used to check if there is any error in the Codeword read in (Figure 3).
Figure 3 LDPC Encode / Decode
If it is confirmed that a read error occurs, the first phase of Hardbit Decode error correction will be done. Hardbit Decode's error correction capability is similar to the traditional BCH, at this stage to check through the bit error data, if in the Hardbit Decode phase Unable to correct the error, it will enter the second phase Softbit Decode.
In the Softbit Decode phase, the error correction is mainly performed through the LLR (Log-likelihood Ratio) correspondence table. The LLR correspondence table records the probability of errors occurring in each bit by means of probability statistics. An error occurs by using the LLR correspondence table Of the data error correction to NAND Flash supplier group of electronic, for example, the company for 3D TLC Flash, with the corresponding LLR table and with digital signal processing (DSP) module, according to the accumulated error correction experience, Dynamic generation of updated LLR table to get the best decoding results and error correction capabilities to improve error correction performance.
The design of the parity-correcting matrix in the LDPC process can affect the error-correcting efficiency of the LDPC. If the optimized parity-correcting matrix is not designed, there may be fewer but not corrected errors in the number of ECC errors and may also occur when the number of ECC errors is larger and the number of corrections The ability to weaken the phenomenon.
During the error correction phase of entering SmartECC, the error correction is based on Page Flash. When each page is written into NAND Flash, the data written into the page is also sent to SmartECC engine for encoding. After encoding, Generate corresponding ECC (ECC Parity), and the correction code will be written into the NAND Flash along with the written data. When data errors can not be rebuilt through the LDPC Hardbit / Softbit Decode flow, SmartECC engine The resulting calibration code, to do data recovery.
Three-phase error correction to ensure NAND Flash performance
Today, NAND Flash manufacturers have successively introduced 3D NAND Flash, which has surpassed 2D NAND Flash in 2017 to become the mainstream market process. NAND Flash controller needs to have more stable management and more comprehensive correction Wrong ability, in order to fully play 3D NAND Flash product features and benefits.
3D TLC Flash relies on the NAND Flash controller for higher error correction capability due to the process architecture. The three-phase error correction protection mechanism provides an efficient and low-power data error correction solution for NAND Flash data errors , Effectively extend the service life of 3D TLC Flash SSDs and enhance product reliability.