• Ncore Cache Consistency Interconnection version 2.0 and 2.2, which includes Resilience features (ISO 26262 functional safety), innovative configurable cache options, and 0 to 16 cache coherency ports • PIANO 2.2 assists with timing closure ( PIANO 2.2 timing closure assistance, including architecture floorplan generation, production floor map entry and modification, enhanced automated pipelining, and support for early access cache coherency. In addition, Arteris IP introduced FlexNoC with better performance Sexual Interconnect Version 3.5, which allows users to design system-on-chip (SoC) interconnects operating at 2 GHz or higher.
On the corporate front, Arteris IP named Ty Garibay CTO and expanded the company's engineering and customer support team, moving to a new corporate headquarters in Campbell, California and opening a new engineering facility in Austin And doubled the size of the Paris office. "Arteris IP President and Chief Executive Officer K. Charles Janac said:" Arteris intellectual property products were ordered to the highest level in the company's history in 2017. "He said that, 'Our interconnection technology for resilient autonomous systems supports our customers' mission-critical electronic devices for markets such as automotive ADAS, driverless cars and other autonomous vehicles. "In China, we are engaged in deep learning of system-on-chip We are particularly pleased with the customer's adoption of our product. '