Industry partners and researchers have made significant strides recently in applying machine learning to the thorny chip design issue, as demonstrated by a panel discussion at DesignCon this year showing the use of human labor in electronic design automation (EDA) Intelligence (AI) is a very popular topic at present. Not only do many related papers have been published at the conference, but many attendees have also been attracted to the panel discussion.
Over the past year, CAEML has added four more new partners, a research team of 13 industry members and three universities that is continuing to expand the breadth and depth of its work .
"Last year, we focused mainly on signal integrity and power integrity, and this year we divided the product portfolio into systems analytics, silicon, and chipsets," said Christopher Cheng, a distinguished technical expert at Hewlett-Packard Enterprise (HPE) and member of CAEML. Layout and credible platform design have made the most progress in the diversity of research. '
Paul Franzon, an Outstanding Professor at NC State University, said: 'The Bayesian Optimization and Convolutional Neural Networks (CNN) have also significantly enhanced functionality in DFM, and we started Consider using synchronous learning in the design process. "North Carolina State University is one of CAEML's three partner universities.
Madhavan Swaminathan, a professor at the Georgia Institute of Technology, another CAMEL-affiliated school, said: 'One of the challenges we face is getting the company's data because most of their data is proprietary, So we've come up with several handling mechanisms that are all working well, but are still much longer than we expected. "
CAEML was founded by Analog Devices, Cadence, Cisco, IBM, Nvidia, Qualcomm, Samsung and Xilinx Xilinx) support from nine vendors, beginning with areas of interest include high-speed interconnect, power transmission, system-level electrostatic discharge, IP core reuse, and design rules check.
EDA vendors such as Cadence Design Systems began researching machine learning as early as the early 1990's David White, senior director of research and development at Cadence, said that the technology was first introduced into its products in 2013 using a version of Virtuoso that leverages analytics and Data mining creates a machine learning model for parasitic parameter extraction.
To date, Cadence has provided over 1.1 million machine learning models to its tools to accelerate long-term computing, and the next phase of product development is layout and routing tools that allow it to learn from human designers and White suggested that these solutions could use both local and cloud-based processing to take advantage of parallel systems and large datasets.
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Sashi Obilisetty, Synopsys' director of research and development, said global routing tools using existing algorithms have reached their limits at advanced process nodes, so they began to reduce chip data rates for timing closure.
She added that Taiwan Semiconductor Manufacturing Co. last year used machine learning to predict global winding, resulting in a 40MHz increase in speed; Nvidia used machine learning to provide full coverage of the chip design while reducing simulations.
The experts who participated in the panel said they saw many opportunities in the industry for using machine learning techniques to automate specific decisions and optimize the overall design process.
Specifically, researchers are exploring opportunities to replace today's simulators with faster AI models, says Georgia Institute of Technology Swaminathan, a relatively slow simulator that could lead to timing errors, analog circuit imbalances, and chip re-streaming (respin) modeling problems.In addition, machine learning can replace IBIS behavioral modeling in high-speed interconnection.
In addition to the neural network models promoted by Amazon, Google and Facebook photo search and voice recognition services, chip researchers also use data mining, statistical learning and other tools.
North Carolina State University's Franzon reported using a proxy model to optimize the final physical design in four iterations, compared with engineers having to do up to 20. A similar technique was used to calibrate analog circuits, Channel Interconnect Set Transceiver.
AI can set dozens of options in EDA tools (sometimes referred to as knobs) to help speed up the automation process. "These tools have knobs that are sometimes unclearly defined and often have a fuzzy relationship with the expected results. '
HPE currently uses neural networks and hyperplane classifiers to predict fault scenarios on the fly based on data such as voltage, temperature, and current of solid-state drives (SSDs).
Cheng said: 'The training requires a huge amount of data, and so far the classifier is static, but we want to increase the time dimension using RNNs instead of just good / bad tags, There is a time-to-failure tag, and in the future we want to extend this work to more parameters and to general system failures. '
Compile: Susan Hong