Power Sequencing Avoids Damages Many techniques are available to control the startup sequence and timing of multiple current rails in today's large, system-on-a-chip FPGAs, and it is important to follow the correct sequence specified by the device manufacturer to avoid device draws Excessive current causes damage.
Some methods control the Enable pin of the next supply in the sequence by manipulating the power good output of each converter. If a relay is needed, a capacitor can be inserted. Another alternative is to use the reset IC, Powering up to the desired voltage starts with the next converter Each of these methods has some drawbacks and none of these methods control the order in which the power is turned off.The closing of the rails in the correct reverse order is as important as turning on the power in the correct sequence Is to ensure that the device can work safely.
Using a dedicated power sequencing IC is more stable to ensure that it is in the correct sequence. The IC can be programmed to send Enable signals at the desired time points. Figure 1 shows how the multichannel sequencer manages FPGA core logic, peripherals, and I / O fields, the power-down sequence is still difficult to control because the decoupling capacitors on each rail may still have residual charge after the converter is turned off, and the residual time may not be constant, and up to a maximum of one can be connected per rail Total decoupling capacitance of 20mF.
Sequencer Maintains power off control
Using a circuit with a known time constant to proactively discharge the decoupling capacitor, the sequencer maintains the proper power-down sequence by temporarily inserting the discharge resistor into the series capacitor Figure 2 shows how the minimum necessary Under the device, a carefully selected MOSFET is used to insert the resistor into the circuit.
The circuit in the figure assumes that the DC-DC regulator can not continuously generate output after it provides a shutdown signal. If the DC-DC regulator's output continues to supply power after a shutdown command is received, an additional relay is required to activate the discharge circuit .
The value of R2 must be chosen to ensure proper discharge time so that the sequencer can be shutdown within an acceptable time interval Also note that the resistor must be large enough to avoid excessive current spikes and avoid Causing EMI problems, and transient thermal stresses on Q2 and decoupling capacitor banks. In practice, there are additional important parameters to consider when choosing R2 values, such as the on-resistance of Q2 (RDS (ON)) and the capacitance of the capacitor bank Equivalent series resistance (ESR).
The power sequencer output voltage threshold should be referenced when selecting MOSFET Q1. The device selected should have a high gate threshold voltage (VGS (th)) to keep the sequencer output high while still shut down, Note that the VGS (th) will decrease as the junction temperature rises. The sequencer operation selected in this example operates at a supply voltage of 5V and the minimum specified high potential output voltage is 4.19 V. The VGS (th) of Q1 is between 60 ° C The ambient operating temperature must be greater than 0.9V to ensure proper operation. In addition, the gate should be pulled down to the source using a 100kΩ resistor to avoid misinterpretation. View the normalized VGS (th) versus temperature graph in the MOSFET data sheet to show that the Diodes The company's ZXMP6A13F meets the requirements: to ensure that the minimum VGS (th) at room temperature is 1V, to 60 ℃ then dropped to 0.9V or so.
In this example, we assume that the sequencer must turn off a total of 10V of rails within 100ms. Therefore, the decoupling capacitor bank for each rail must be discharged within 10ms. The goal is to achieve three times the RC time constant of 8ms To ensure that the capacitor discharges below 5% of its full voltage in the required time To calculate the RC constant, the capacitor bank RDS (ON), parasitic line resistance, and ESR must all be taken into account with resistor R2.
Assuming that the ESR of the capacitor and the line resistance do not add up to more than 10 mΩ and the total decoupling capacitor bank has a capacitance of 15 mF, the appropriate values of RDS (ON) and R2 can be obtained from the following equations:
3x (10mΩ + R2 + (1.5 × RDS (ON)) × 15mF = 8ms
Assuming R2 = 50mΩ, the RDS (ON) of power MOSFET Q2 must be less than 80mΩ at VGS = 4.5V and ambient temperature of 25 ° C.
The effects of temperature-dependent variations and bulk variations of RDS (ON) should also be taken into account when selecting MOSFETs. RDS (ON) may vary as much as 15mΩ beyond the expected operating temperature range with a 4.5V gate drive. Approach is to determine that R2 is about twice as large as the maximum RDS (ON) specified by the manufacturer of the selected MOSFET, or if Diode's DMN3027LFG N-channel MOSFET is used at 50mΩ, this device operates at VGS = 4.5V at room temperature RDS (ON) is typically 22mΩ and 26.5mΩ, respectively, so RDS (ON) can vary from 15mΩ to 40mΩ with a discharge time of 3.9ms from 95% (3 times RC) and a worst case 20mF The discharge time of the capacitor bank may be extended to 5.4ms.
Evaluate maximum single pulse to protect MOSFET safety
The DMN3027LFG consumes energy within the capacitor as a function of current and voltage over time, so there is a need to evaluate the maximum single pulse for the power MOSFET to safely handle while ensuring that the junction temperature does not exceed the absolute maximum rated typical TJ (max) = 150 ° C. For detailed information, see the Safe Operating Area (SOA) in the MOSFET datasheet. The SOA should be based on the ambient operating temperature required for the MOSFET gate driver application. When discharging a capacitor bank with a 0.9V charge, The accepted SOA curve should indicate that the single pulse spike current is at least 1V and the pulse width is between 1ms and 10ms. SOA should be suitable for typical application ambient temperatures and should be installed under a minimum heat sink (also referred to as MRP) Of the circuit board, which is assumed 60 ℃.
In addition, the power dissipation of the DMN3027LFG (Q2) MOSFET and the R2 series resistor needs to be considered. The worst case scenario is to charge and discharge the capacitor in a short period of time. Assuming, in the worst case, the power sequencer can enter a continuous loop , Starting the DC-DC regulator every 20ms and then de-asserting (10ms enabled + 10ms disabled), the DMN3027LFG and R2 will have about 0.5W of power dissipation.This is the known total energy stored from the capacitor bank Calculated every 20ms discharge:
P = E ÷ t = ½ CV2 ÷ 20 ms = 500 mW (assuming C = 20 mF, charged to 1 V)
The DMN3027LFG has a maximum RDS (ON) of 40mΩ and therefore consumes 222mW and 278mW for Q2 and R2 respectively. If RDS (ON) is lower than 15mΩ, R2 consumes 385mW and therefore consumes 0.5W Resistance of the rating.
In normal applications, the ambient temperature is expected to approach 60 ° C while the DMN3027LFG has a junction-to-ambient thermal resistance (RθJA) of 130 ° C / W with a minimum recommended pad configuration and a TJ of nearly 90 ° C at 222mW. (max) = 150 ℃ There is a lot of space reserved.
The actual operation of the circuit is shown in Figure 3. The spike current is limited to about 12.5A and the capacitor bank discharges from the initial 1V state to 5% for about 4ms, which is close to the theoretical calculation.
