From left to right: Shay Wolfling, Rick Gottscho, Mark Dougherty, Gary Zhang, David Shortt.
Moderator: Looking 10 / 7nm, will enter into 5nm or 3nm it? This is more difficult than we expected? Is it possible?
Dougherty: Although we have not found a more suitable solution, we believe it is achievable, but it is not expected that such a goal will be achieved in a straight line, nor will it be hyperbolic or exponential.
Gottscho: I agree. The path to 5nm is obvious. FinFETs will be extended to at least 5nm, may also be extended to 3nm. There will be other solutions, there will be new materials, there will be more challenges. We know that production 5nm design rules 150nm high fins.But manufacturing is one thing, how to prevent them from collapsing is another matter.There are many challenges, but we are still firm.
Shortt: About 30 years ago, I read an article that clearly explained why it is impossible to use imaging techniques to make devices that are smaller than the wavelength of light, and we all know what that means, The bets are all wrong, and now it looks like we can do it. It looks like we can not do a few generations of craftsmanship, but in the end we can always do it. As a tester, I was surprised that these devices are manufacturable With 3D NAND, we can make these amazing products.
Zhang: We know from the customers on the supply chain that microfilming is not over yet. In photolithography, we made a lot of effort on the EUV to bring the new process node to fruition. On the roadmap, high- NA is an extension, so we do have a solution in terms of printing and graphics, and we face a bigger challenge in how we manage complexity and cost, but we do.
Wolfling: I agree, but the problem is not easy to deal with because it works in many ways. There's space to extend the transistor, or it could be nanoflakes, but where is the intersection? 3nm or 2nm? To some extent There are industry spans that may occur in EUVs and may also occur in finFETs. The problem is where it will happen.
Moderator: However, we have some major issues to solve. There are interconnections, RC delays, there are many problems no one can solve. For example, in the logic of the manufacture and measurement, what is the new opinion?
Dougherty: The challenges I see are actually the number of options and the technology used for mass production is increasing.Reviewing the past generations of crafts you know more or less about the materials and basic structures you are going to use Now, when you look forward At 7nm and beyond, our vendor road map shows that it could be any of these 10. The answer is some combination of them, but filtering out these different options on the advanced nodes requires more work, It may not be a single solution, and for the longest time in the industry, everyone is consistent at the last minute of the same solution. There may be some disagreements, such as the aftermath of metalworking.
Zhang: The problem is not that you hit the wall, but that you have a lot of roads. The question is how we explore all this. From the beginning they may be promising, but hard to say which one is cost-effective and which one is fine This is part of the investment needed - to investigate different materials and different directions, and I do not think the problem is that we are facing a dilemma.
Moderator: We are faced with many choices, right?
Gottscho: Yes.
Zhang: We discussed the issue of measuring the size below a second, and now we can do it in 3D, so we have a solution for the measurement, and we have a way to solve all the problems we want to measure, which is still Is a problem
Shortt: What I have seen over the years is that from concept to actual shipments, the end-to-end cycle time is getting longer and longer, so we need to start earlier. We have several generations of processes that are cross-cutting, at any time We are getting a lot of good ideas, but we have to start thinking about them earlier and do the technical downsizing to find out what works and what is not, and then to continue, so for us, End-to-end costs are getting higher and higher.But with proper management, you reduce the technical risk from the beginning, quickly abandon those not feasible ideas, and then retain those useful ideas.
Moderator: Another logic involved in all of this is 3D NAND. We've expanded to layer 48. Will it continue to expand, or will there be limits?
Gottscho: It is expected to continue to rise for some time, and I am optimistic about the future because now we have seen a 256-layer approach, but I think people in the semiconductor industry need to be cautious and it is already very challenging to reach 128 The pressure on the mask is a big concern, and it would not be appropriate if the wafer looks like a potato chip. Another big problem is the etching of the hole, which I saw most in the 35 years of etching Challenging is the alternating layers of oxide and nitride, or oxides and polymers, with aspect ratios close to 100: 1. But at this point we already have a solution line and we're working on three generations of technology It will achieve large-scale production in the next 10 years.
Shortt: Do you see the future of 3D NAND in 100 steps to complete the etching?
Gottscho: This is hard to say, and our strategy is to move the etching technology to the maximum aspect ratio because we believe it is advantageous to do as much customer benefit as possible among our customers.
Wolfling: Once you start stacking, if you have 3 to 4 generations and stacking them together, this is not worth the money, and the more you push the etch, the more time you spend in this direction.
Moderator: Another key part of the von Neumann architecture is DRAM. Can we go one step further and apply the 1x technology to 1y, or do we need to turn to other technologies like Phase Change Memory or STT-RAM?
Zhang: Our clients are moving along the 1x, 1y, 1z paths trying to squeeze out another nano, which has been around for a couple of years and that will continue. How far is unknown, except that we have not seen yet another device that can replace DRAM, and we did see XPoint as another viable memory solution that plugs into the current memory architecture.
Dougherty: But do you think there is another time-to-go option? Although we do not know what the intersection points are, there's certainly a lot of work to do in all of these different storage technologies.
Zhang: That is why people are looking at XPoint and other storage technologies to see if they can push this out in terms of cost, performance and endurance, but it remains to be seen how DRAM can fit.
Shortt: We saw KLA-Tenco's prediction that 3D NAND will be used much earlier, but 3D NAND can push one or two generations beyond what many would have expected, which delayed the start of 3D. It happens to DRAM too, and they push as much as they can.
Gottscho: I see the difference between DRAM and 2D / 3D NAND dynamics because 3D NAND is ready before the 2D NAND runs out, and it looks like there is no DRAM replacement right now. Whether STT-RAM or phase change memory Or resistive RAM, none of which matches the speed or endurance of the DRAM. The necessity is the mother of invention, and we see at least two generations after 1x, and we hear about 1a. DRAM still has its life, But it becomes harder and harder. MRAM may be used as an embedded logic memory component. It does not look like a viable alternative to high-density DRAM.
Shortt: We have not seen a lot of demand for measuring these new structures, and we've seen some but not many.