At the recent 2017 International Electron Device Meeting (IEDM) in San Francisco, USA, Intel revealed details of the plan to use cobalt material for some of the interconnects at the 10nm process node GlobalFoundries describes how the company is making its first battle with its EUV lithography technology for its 7nm process node.
Intel said it will use cobalt on the bottom two layers of the 10-nm node interconnect to achieve 5 to 10 times better electron mobility and twice as much via resistance. Market Research Institute Chairman VLSI Research Chief executive G. Dan Hutcheson said this is the first time chipmakers have shared plans to apply cobalt materials to process technologies that have long been considered potential dielectric candidates.
Globalfoundries has previously said that EUV will be used at the 7-nm node, which introduces a fully immersed optical lithography-based platform designed to introduce EUVs at specific levels to improve cycle times and manufacturing efficiencies; the company In an interview with EE Times, Gary Patton, vice president of technology and global R & D, said there are still some issues that need to be addressed in the EUV, including the pellicle and detection technology. Globalfoundries is currently installing at the Fab 8 fab in northern New York The first EUV volume production tools.
In an interview with the EE Times, Hutcheson said he was impressed with Intel and Globalfoundries technical briefings on IEDM, but added that the lack of technical detail is still disappointing for hard-core technologists, but chipmakers usually Hoping to retain proprietary know-how: "These people will not be willing to give up anything." He also said both companies have demonstrated how new technology can increase logic-transistor density by more than double the previous generation, This means that industry still follows the footsteps of Moore's Law.
Intel and Globalfoundries have previously released the latest process technology; Intel's 10-nanometer node debuted in March using self-aligned quadruple patterning (SAQP) technology with a fin width of 7 nm and a height of 46 Nano, 34 nm pitch FinFET structure.
Globalfoundries, which debuted the 7nm process for the first time in September using SAQP to fabricate fins and double-metallize, is said to have an increased logic density of 2.8 compared to the 14nm process the company licenses from Samsung 40% higher performance, and 55% lower power. Both Intel and Globalfoundries processes support multiple voltage thresholds.
Dielectric material ignites new war
Intel will use contact metallization with cobalt at the 10-nm node, which could become a differentiating feature on the battlefield of advanced semiconductor processes; Globalfoundries will continue to use copper at the 7-nm node for the past few nodes in the semiconductor industry / Low-k dielectrics.
Basanth Jagannathan, a Patient at Globalfoundries and a prominent member of the technical team responsible for introducing 7-nanometer technology, said in an interview with EE Times after the IEDM briefing that the continued adoption of copper / low-k materials because of their reliability benefits reduces technical complexity and performance Rate risk: "There is still plenty of room for copper material utilization."
Another notable difference between the Globalfoundries process technologies is the use of dual graphics in the back-end metallization, which Jagannathan explains in his briefing, "The use of SAQP can provide a density advantage but can severely impede the customer's agility." We provide Is foundry technology, "he said:" There is a need to cater for a wide range of designs. "Pattom told EE Times that the latter part of the process continues to adopt a double graph." It does not mean that we do not have enough density and not everything Spacing is concerned; we are in a somewhat different approach to achieving the density target. "
At IEDM, in addition to disclosing 10-nanometer process details, Intel also provided another paper that describes the 22-nanometer FinFET low-power process technology and impresses VLSI Research's Hutcheson; he said the process is considered a cell phone Ideal for RF Applications - Describes a new trend in which foundry operators are "going backwards" to optimize older process nodes.
Globaltons Patton at this year's IEDM also received the IEEE Frederik Philips Award in recognition of his influence on the industry and the leadership of the development of advanced microelectronics technology to promote collaborative research and development achievements; he said he was the first time I participated in the IEDM students And it was already 35 years ago.
Globalfoundries technology chief Gary Patton