The semiconductor industry's journey to the 10 nm process has been long and arduous, but Intel appears to have found ways to play the advantages of this process, and the upcoming first Cannon Lake notebook computer (NB) will show results. Following the release of 14 nanotechnology by Intel 3 years ago at the Conference of International Electronic Components (IEDM), and after the presentation of Cannon Lake NB in ces nearly a year ago, Intel first started to publicly explain the details of the 10 nm process in iedm in 2017, The results of encapsulating 100 million transistors in the area of 1 square centimeters of grain range are claimed to be the highest-density CMOS transistors to date. At the beginning of the year, at technology and manufacturing day, Intel described the basic function of 10 nanotechnology, the spacing of this process fin is 34 nm, the gate spacing is 54 nm, and the minimum metal spacing is 36 nm. Since 180 nm, Intel has continued to reduce the size of each generation of SRAM units by 0.5 times times, 10 nm to 0.0312 square microns. This size is similar to the wafer plant for Apple, Nvidia and Qualcomm (QUALCOMM) with 7 nm fabrication. Intel offers more manufacturing steps, features and material details on the iedm. The 10 nm process uses Intel's 3rd generation 3D fin-type transistors (FinFET), when the fins are thinner and higher, the performance will be better, 10 nm process fin width is only 7 nm, the height of 46 nm (previously Intel was mentioned to be 53 nm), the height can be adjusted with different applications, scaling range is 5 nm. The standard 193 nano-invasive micro-film (immersion lithography) tool of the Intel miniature process is the so-called self aligning four-weight pattern (self-aligned quadruple patterning; SAQP) to make fins, the process adds four extra steps to increase the density. Intel also reduces the number of fins in the standard unit (cell) and refers to two new techniques to increase the density. The first is the elimination of the pseudo gate of the boundary active unit (dummy gate), the other is the active gate contact (contact-over-active-gate, COAG), the direct placement of the intermediate layer (via) into the initiative Gate area, which requires three additional steps, The unit area is reduced by 10%. According to Intel's estimate, Intel's density accelerated, from 45 nm to 22 nm twice times to 14 nm and 10 nm to 2.7 times times higher. However, Intel appears to be planning to speed up further, said Chris Auth, vice president of Technology and Manufacturing group, that the grain density will increase 1 time-fold every two years in the future. As the fins are reduced and the resistance is low, the performance of Intel's latest process is further enhanced, previously said to be 14 nm, 10 nm performance will increase by 25%, and power consumption is reduced by nearly half. But on IEDM, Intel says 10 nm drive currents are 71% higher than nmos transistors, 35% higher than PMOs. Intel did not say when the first 10-nanometer processor was launched, but that the first family member, Cannon Lake, might appear in a notebook computer in 2018.
