According to DRAMeXchange, a research institute for semiconductor storage, the momentum of SSD shipments is still upscale today, especially in the consumer SSD market, where its growth momentum is expected to continue into 2020 (Figure 1 ).
Figure 1 SSD shipments statistics and estimates
Source: DRAMeXchange (2017)
SSD interface continues to evolve PCIe scalability over SATA
SSD physical interface support are mainly Serial Advanced Technology Attachment (SATA) and Peripheral Component Interconnect Express (PCIe) two of which SATA Gen3 is the most popular SSD transmission interface on the market, the theoretical transmission bandwidth of 6GT / s.In the past In the past few years, SATA Gen3 data transmission bandwidth, compared with the traditional hard disk has obvious advantages, prompting SSD's market share year by year.
At the same time, NAND Flash process and related technologies are also evolving, NAND Flash and controller transfer interface standard, from the past Legacy Mode to the current Toggle 2.0 / ONFI 4.0 speed has been greatly improved, making the past SATA Gen3 the most popular in a few years, the theoretical bandwidth has become a major bottleneck in the development of SSD, PCIe SSD also took advantage of the rise.
With PCIe Gen3, its theoretical bandwidth can reach 8GT / s (1-lane), in addition, PCIe interface provides excellent scalability, the theoretical transmission bandwidth will be multiplied with the number of Lane (Lane) PCIe interface Can be expanded from 1-lane up to 16-lane, the transmission bandwidth can be said that SATA is not in the same grade.
In addition to the above mentioned physical interface support evolution, the transfer protocol between the SSD and the host also changes from the earlier Advanced Host Controller Interface (AHCI) developed for SATA devices to the Non -Volatile Memory Express (NVMe), Table 1 briefly contrasts the major differences between AHCI vs. NVMe.
In other words, NVMe's transport protocol, after the evolution of the PCIe interface, once again liberated the potential of SSD as a storage medium device with NAND Flash to push SSDs to the next generation.With the popularity of NVMe transport protocol in the SSD market , Consumer-grade PCIe SSDs are expected to reach about 50% market share in 2018.
In the consumer SSD market, there are several key factors that can directly affect product sales figures.
price
Generally speaking, NAND Flash is the most expensive component of the entire SSD. With different manufacturers' SSD configurations, the cost of NAND Flash can reach 80% to 95% of the total Bill of Material (BOM) cost of the SSD.
However, NAND Flash is the primary storage configuration for SSDs and is an integral part of this strategy, so it is a way to save money and reduce the cost by removing unnecessary components from other SSDs.
And all manufacturers first think of the object of removal will be dynamic random access memory (Dynamic Random Access Memory, DRAM), a rough point of view, a 4Gb DRAM chip that is about 3 to 4 dollars.It is obvious that if the DRAM Can be removed beyond the BOM of the SSD, which can be quite significant for the cost and price of the SSD.
Power consumption
Power dissipation is another big consideration for SSD makers, especially for SSDs targeting PC OEMs, which typically account for about 5% to 10% of a portable device % Of the power consumption.
If SSDs can reduce power consumption, they can leave the overall Power Budget to the rest of the components and extend the battery life of portable devices.
Reliability
SSD as the user's storage device, the reliability of the data is bound to be the user's primary consideration.Although today's various error detection and error correction technology is increasingly developed, but if a loss of power that is removed from the DRAM, You can further reduce the possibility of user data loss or distortion.
performance
Even though all of these factors are a major consideration for SSD manufacturers and users, efficiency is still strong enough to affect consumers' willingness to purchase SSDs. If an SSD has no DRAM to serve as a cache, its performance will inevitably be significantly affected , Which is why DRAM-Less SSDs are not popular in the PCIe SSD market today, and today consumers who purchase PCIe SSDs mainly need high-speed access and remove the overall DRAM performance for SSDs Instead, it is discounted.
HMB boosts DRAM-Less SSD performance
Fortunately, the NVMe Association also observed this trend in the consumer SSD market by developing the Host Memory Buffer (HMB) function in NVMe Specification v1.2 proposed in 2014 to improve the overall performance of the DRAM-Less SSD, and to expect the consumer Level SSD solution can further reach the balance between price and performance.
Host Memory Buffer, as the name implies, provides a mechanism for the host to use the memory resources that are currently not needed and provide it to the SSD through the NVMe protocol. As a result, the DRAM-Less SSD can be used by itself And DRAM is not configured to obtain additional DRAM resources to improve performance as a cache.When the SSD obtains HMB resources configured by the Host in a specific situation, the SSD controller places those information in this area Objectively speaking, this is determined by the firmware built into each SSD controller.
However, taking into account the actual status of SSD products in the past, the Logical to Physical Address Translation Table (L2P Mapping Table) is the most likely system information to be placed in the HMB.
In simple terms, the L2P Mapping Table records the mapping relationship between the logical page's (Page) position and the physical (physical) page position. Whether the SSD needs to be read or written, Will need to access a certain amount of L2P Mapping information, so placing an L2P Mapping Table in HMB reduced access time to improve SSD access speed seems quite reasonable at first glance.
How can the DRAM-Less SSD performance be affected after the actual HMB design is introduced? The following is an example of how DRAM-Less SSD performance can be affected by a simplified computational model (4-channel SSD with no configuration DRAM + transport interface: PCIe Gen3 2-lane + 3D NAND Flash) derived from the overall performance trends.
In order to be able to simply show the difference in performance caused by turning on HMB, let's assume that the size of the HMB that the SSD can get from the Host is fixed at 128MB and can not be reclaimed. From Figure 2, we can clearly see that in sequential reads and writes Opened under the HMB performance after the operation, and not much improvement. Considering the nature of the HMB is still volatile memory, used to store the user to read and write data, the proportion of space is usually not too high, the vast majority as Storage L2P Mapping Table cache (the implementation will vary with the design of various SSD vendors vary).
Figure 2 Enable HMB sequential read and write performance comparison
The overall performance is not easy to improve HMB design has a mystery
Generally speaking, the time to read data from RAM is far less than the time it takes to read data from NAND Flash (ns vs. us), so if the algorithm can be designed and promoted using the appropriate algorithm, the L2P Mapping Table Hit rate (Hit Rate), will be able to improve the overall performance to some extent.
In sequential read and write operations, because the data read and written by the user is continuous, the logical relationship between the physical layer and the physical layer will also be continuously distributed. Therefore, the L2P Mapping Table does not need to be frequently re-read from the NAND Flash Caught inside the HMB.
In other words, for sequential read and write operations, because the Hit Rate of the L2P Mapping Table must be very high, there is a very low chance of re-fetching the L2P Mapping Table. Therefore, even if the L2P Mapping Table only has lower cost depending on the controller's embedded cost Of Static Random Access Memory (SRAM) to store a small amount of L2P Mapping Table is enough, which is why HMB can store more Table, the overall performance will not have a significant impact.
When a user performs a random read, the next data location to be processed is unpredictable for the SSD controller, meaning that the Hit Rate of a small number of L2P Mapping Tables temporarily stored in the SRAM is less than Sequential reading and writing will be significantly reduced.
In this case, random access performance can be significantly improved if additional L2C mapping tables can be obtained for additional L2P mapping tables in order to increase Hit Rate and thereby suppress the need to recrawl information from NAND Flash.
With this easy-to-compute model, performance improvements based on HMB can be as good as 40%, even for random reads across the entire Full Disk. In addition to this, another trend we can observe is : The performance improvement caused by HMB will be more pronounced as the overall SSD capacity increases (Figure 3).
Figure 3 before and after enabling HMB 4KB random read performance comparison
This is because when the user performs a random read, if the test data is sufficient, the larger the capacity of the DRAM-Less SSD, the lower Hit Hit will be stored in the cache Mapping Table under the same SRAM size configuration At this point, if the HMB resources released by the Host to the SSD can be obtained, the performance of the HMB with the appropriate Flash Translation Layer (FTL) architecture can be greatly improved.
The performance improvement trend of random write of 4KB data by HMB under the same DRAM-Less SSD estimation model is shown in Figure 4. The write behavior is more complicated for the SSD controller than the read .
Figure 4 before and after enabling HMB 4KB random write performance comparison
In addition to reading the L2P Mapping Table while writing data, the controller firmware needs to modify the contents of the L2P Mapping Table (logical-physical mapping table needs to be modified accordingly) and save it back to NAND Flash Inside, to complete the entire data write action.
If there is not enough buffer space to store the L2P Mapping Table, the controller will need to access the NAND Flash block more frequently to obtain every L2P Mapping Table information to be written in the case of random write.
In addition, it generally takes much longer to write data to each NAND Flash than the time it takes to read the data (ms vs. us), so if the SSD is not configured for DRAM as a cache, the random write performance Will be greatly affected.
If DRAM-Less SSDs are designed to support HMB, which in turn gets additional DRAM resources from the host, it can yield even more significant benefits.
Using the same estimation model, the DRAM-Less SSDs support the HMB mechanism for random write testing of the entire SSD storage area, resulting in performance gains of up to 4x to 5x.
HMB size affect read and write performance SSD design must be more comprehensive
The DRAM-Less SSD performance trends described above are based on the assumption that the Device end can continue to receive a fixed 128 MB of dedicated memory from the Host end.
However, the actual size of the HMB is dynamically allocated by the Host according to the current usage of the SSD and the demand of the SSD. If the size of the memory resource that the Host can provide now does not meet the demand of the SSD, the SSD does not To use this piece of HMB.
Therefore, when designing the controller firmware of the DRAM-Less SSD, it is best to consider more than one HMB size, so as to improve the user experience by using the HMB.
Based on the same estimation model, Figure 5 shows the result of a 4KB random read / write calculation when the size of HMB is from 0 (without HMB) to 1024MB.
Figure 5 different HMB block size for 4KB random read and write performance
We can observe that while the general performance trend is better with increasing HMB size, SSD performance begins to saturate when enough HMB resources are available, because when enough HMB is available , The SSD Controller can put all the needed system information (including the L2P Mapping Table) for reading and writing into the HMB.
As a result, DRAM-Less SSD performance can be viewed as an optimization result (theoretically equivalent to SSDs that are natively configured with the same DRAM resources.) Therefore, when SSD controller vendors design firmware architectures, they need to consider what The system data structure allows the DRAM-Less SSD to reach its saturation point as soon as possible.
In other words, how to design a set of HMB system data structures in DRAM-Less SSD to support both HMB system data structures, taking into account access speed and memory resource consumption, and even specifically optimizing HMB sizes that are easier to allocate to SSDs from a statistical probability point of view The situation, has become the SSD controller manufacturers in the upcoming debate about the PCIe DRAM-Less SSD product line of the winner.
While performance improvement is certainly what HMB was supposed to do, after talking about performance, we need to go back and focus on the most basic requirement for all storage: Data Integrity.
Let's think about the question: For SSD controllers, is it 100% fully trusting all the information that exists in HMB? In an ideal situation, the answer is yes; in practice, we still recommend Strong enough security mechanism.
When the DRAM-Less SSD is assigned to a HMB resource, what kind of information is stored in the HMB? In fact, the answer to this question varies with the firmware design of each SSD controller, but the data buffer Data Buffers, L2P Mapping Tables, or system information required by the remaining controllers are all possible options.
Some of this information is important or non-rebuildable to the SSD controller, so when NVMe introduced HMB, it required the SSD controller for the supported HMB to be able to guarantee data in the SSD without expecting to turn off the HMB function The integrity of
In addition, unexpected or even illegitimate host-side access or distortion in the data transmission may affect the information stored in the HMB How to ensure the integrity of the data stored in the HMB has become the PCIe DRAM- Less SSD a topic.
Ensuring SSD Data Transmission Integrity The E2EDPP mechanism stands out
In the SSD market, solutions are expected to have the ability to ensure the integrity of data as it travels between the host and the device end. E2EDPP (End of End Data Path Protection) 6) is a fairly popular set of mechanisms for this purpose. When data is read or written, its path travels through different sites, including the Host → PCIe IP → Processor → Data Buffer → Security Engine → Flash IP → NAND Flash, read path is reverse.
Figure 6 End-to-end data path protection (including HMB data path)
The main purpose of this protection mechanism in addition to ensuring data transmission is protected, if the controller RAM movement of data occurs Soft Error, the overall design also has the ability to debug, to avoid the wrong data sent to the host.
Now that DRAM-Less SSDs are able to store specific information on the host by supporting the HMB function, the E2EDPP mechanism should also be extended to ensure two-way transmission of HMB data between the host and the device simultaneously.
How to ensure the data integrity on the HMB information transmission path and look at the design of each SSD controller manufacturer One of the easy concepts is to add HMB data with Parity Check or Cyclic Redundancy Check, CRC) is used to detect if there is an error in the data. Once the test fails, the controller immediately performs error handling.
On the other hand, since the HMB data is stored in the host-side RAM, although the NVMe specification explicitly requires that this block be accessible only to SSDs during HMB startup, any misoperation or even malicious access that occurs on the host side has It is possible to obtain the information stored in the HMB memory and even influence the user according to the obtained information.Therefore, the HMB information to be written to the host can be additionally encrypted and then transmitted first, and when the device side reads back the HMB information, Decrypt and verify the data before using it (Figure 7).
Figure 7 HMB message debugging and encryption and decryption mechanism diagram
I believe in the HMB data integrity and security issues, different SSD controller manufacturers there are a wide range of practices, which approach is the best solution may not be conclusive at present, but it is certain While using HMB to improve the performance of DRAM-Less SSD, the overall system design still needs to strengthen the data protection mechanism to ensure the correctness of user data, so HMB does have a good chance of leading DRAM-Less SSD to the next A realm