In fact, these devices are not real chips but rather system-in-package packages that typically contain one or two ASICs based on the latest semiconductor manufacturing processes (16nm and below) with large processing power and large capacity Ultra-high bandwidth memory (such as the HBM2 stack), all of which are integrated with advanced packaging technology.
Artificial Intelligence (ASIC) -frequency ASICs are gaining traction in the market recently, with vendors such as NVIDIA, Intel, Google and some startups in the pipeline, which are expected to shape billions of dollars in the marketplace in the future. As NVIDIA repositions the GPU as Under the cloud AI engine role, also determined to drive the development of ASIC business, such as Google has now launched the second generation TPU, Intel acquired Nervana chip Nervana acquired, the other by a number of former Google TPU staff founded by the new Enterprise Groq, recently announced that it will introduce its own next-generation AI chips and so forth in early 2018.
Google's TPU, designed specifically for its deep learning algorithm Tensor Flow, is also used in the AlphaGo system, and the second generation of Cloud TPU theory released this year counts 180T Flops to train and run machine learning models Bring a significant acceleration effect, in fact, is also an ASIC chip.Choose to do ASCI customized research and development, on the one hand is financially worry about, on the other hand is also out of the Google needs to provide services, including Google image search, photos, cloud Deep Neural Networks are required for products and services such as Visual APIs, Google Translate, etc. Google has the need and the ability to develop a specialized silicon and have the potential to scale applications that cost much research and development costs.
After its acquisition by Intel, Nervana plans to introduce the first AI-dedicated Nervana Neural Network Processor (NNP) by the end of 2017. Nervana NNP is also an ASIC chip capable of training and executing deep learning algorithms with extreme computational efficiency Intel abandoned the usual caches on the CPU, instead of using special algorithms for chip memory management for specific algorithms, hoping to take the chip's compute density and performance to a new level.
Groq, a startup founded by a former Google TPU employee, plans to release the first generation of AI chips in 2018. The chips are targeted at Nvidia GPUs and are a custom-made chip for artificial intelligence. Computing speed will reach 400 trillion times per second, 8 trillion operations per watt.While the latest generation of Google's TPU reached 180 trillion operations per second, the performance of the Groq chip will be two of the Google TPU More times.
MediaTek will also be the action of MediaTek CEO Tsai Li-line that the layout of ASIC MediaTek will play its existing resources, through the existing team strength, with the active development of ASIC customer needs areas, but after all, has just begun, at this stage will not be too picky customers , Or to the overall business growth as a priority.
Global AI chip first unicorn Cambrian, take the ASIC route.
In fact, due to customization, low power consumption and other benefits, in the field of ASIC ASIC is being used more and more, led to ASIC design and rapid market growth.According to the latest survey by Semico Research, before 2021, artificial intelligence The design of voice-control ASICs is expected to grow at a compound annual growth rate of nearly 20%, nearly doubling the overall ASIC design growth rate (10.1%) between 2016 and 2021 with worldwide ASIC shipments up 7.7% IoT ASIC unit shipments will exceed 1.8 billion units.Semico Research pointed out that the main driver of ASIC growth comes from the industrial and consumer market growth, due to market saturation and reduced demand, the growth of many traditional terminal applications began to slow down, And IOT-related applications are taking off.
Semico Research notes that in addition to IoT and artificial intelligence, ASIC product growth rates associated with smart grids, wearable electronics, SSDs, UAVs, industrial Internet of Things, advanced driver assistance systems (ADAS) and 5G infrastructure are projected Will also be more rapid in the broader market. By 2021, the SoC design project for consumer electronics will grow at 19% CAGR while the Industrial Internet of Things ASIC design project will grow 25%.
ASIC design R & D costs difficult to load, design services bath fire rebirth
In spite of this, the application of ASIC in the field of AI is still facing many problems.
ASICs are custom designed ICs tailored to the needs of the product and are designed and manufactured to meet the needs of specific users and the needs of specific electronic systems. In general, ASICs are specifically enhanced for specific functions, allowing for complex designs as needed, Can achieve higher processing speed and lower power consumption, relatively, ASIC design, manufacturing costs are very high.General IC companies are very difficult to undertake the cost of deep development of ASIC processor chip development risk.First, the future for performance Must use the best semiconductor process, and now with the latest technology to make chips one-time cost of millions, very expensive, even if the money, but also need to set up a team from scratch to design, the design cycle is often very long , It can be said that time to market is too long and risky, and ASIC chips will have to be upgraded to keep pace with new technologies and processes. In addition, ASIC chip designers have fixed their logic early in the development process, There are new ideas in the rapidly evolving field such as AI, and ASIC chips will not be able to react quickly to this. If large-scale With, even if the dollar also developed practical value. Therefore, IC companies generally tend to use general-purpose chip such as CPU, GPU, or semi-custom chip FPGA.
Obviously, as processes continue to escalate, ASIC's tape-out costs have lifted the ASIC's bottom line with the least chip sales, and by the end few other ASIC vendors in the world have been able to afford such huge ASIC chip costs And the risk of failure. With this, ASIC design services once again back to the industry's focus.
For example, eSilicon, a FinFET-class ASIC design services firm in the U.S. fabless industry, announced that it has successfully delivered its own deep learning ASIC to manufacturers for release. ESilicon said this ASIC adopts custom IP, advanced 2.5D packaging process, And is the company's first production chip using TSMC's 2.5D CoWoS packaging technology, said Dr. BJ Woo, vice president of TSMC's business development. The TSMC CoWoS packaging technology addresses the need for deep learning applications for such chip designs. This advanced Packaging solutions can achieve high performance and integration needs to meet the eSilicon design goals mentioned in the previous Google TPU, Nervana NNP, Groq forthcoming first generation AI chips, are sent by the ASIC company to manufacture and TSMC manufactured.
At present, the development of artificial intelligence ASIC is still at an early stage. The fundamental reason is that once the ASIC is designed and manufactured, the circuit is fixed and can only be fine-tuned and can not be drastically changed. However, the cost of hardware R & D and manufacturing is very high. Is not true the market is not clear, companies are hard to rush to try.In addition, can be designed for artificial intelligence chip company must have both artificial intelligence algorithms and chip development company, high barriers to entry.Therefore, AI algorithm + ASIC design services + Foundry's business model is well developed, allowing more and more AI ASIC to come out one after another and development.
Foundries here, there are many foundries around the world, but because of the difficulty is too high, can do AI system package manufacturers are not many, TSMC, Samsung and the core are in the list of the list.So, what is the design of AI systems Packaging? You need to see which vendors are really good at 2.5D integration and have the key IP (such as the HBM2 physical layer interface and high-speed SerDes) necessary for the design. HBM2 PHY and high-speed SerDes module implementation of the package between the various components of the system Mission-critical communications. These are all very harsh challenges in analog design, and buying IP from an ASIC vendor can minimize the risk. All three of the key technologies mentioned above are addressed by eSilicon, who specialize in ASICs in these areas Not many, but because of the artificial intelligence market may be explosive growth, so these ASIC vendors will benefit.
Taiwan also has a large number of IC design services companies, ASIC business in the artificial intelligence market driven again, and the industry is expected to boom this picture is expected to last a long time. TSMC bold prediction 2020 high performance computing (HPC), AI related chip performance Up to US $ 15 Billion, Idea and Core, Wisdom also favors the global demand for ASIC chips from AI customers around the world and is expected to continue for a while starting from 2017, with emphasis on advanced process technology, extremely complex chip design, and high efficiency With low power consumption, it will be a new blue ocean market for IC design service providers.