Different Access Technologies What Will Change When Dynamic Random Access Memory (DRAM) Is Enthed? When storage cells in a DRAM are added with control and data endpoints, Is called a 1T1C DRAM cell. The control endpoint, ie, the word line (WL), is used to transmit the address signal. The data endpoint, that is, the bit line (BL), is used to transfer data values.
Array structure differences
For a long time, the bit lines among the DRAM cell arrays were configured using a differential pair pattern, so the bit lines were divided into '+ BL' and '-BL'; this array Structure named differential storage array (Differential Storage Array), including the array structure of the DRAM chip called differential DRAM chip.Compared to the differential storage array, the new access technology can use a single-ended style to Configuration, so the bit line is 'BL'; This paper named the array structure as a single-ended storage array, DRAM array containing this array structure called single-ended DRAM chip.
The circuit diagram of the memory cell is shown in the upper left of Fig. 1, which is the memory unit of the 1T1C DRAM chip In Fig. 1, in order to clearly compare the difference between the differential memory array and the single-ended memory array, the upper half Into a differential storage array, and the lower half of the drawing into a single-ended storage array.This is the address space is set to 4, which is connected to the addressing circuit of the wire is WL0 to WL3. Connect the data transmission circuit The lead is BL00 (+ BL) and BL10 (-BL) for a differential storage array, with a data width of two and an even number, but the single ended storage array ends in BL0 with a data width of 1, which can be odd numbers Differential storage arrays have complex wire connections and must be interleaved with address lines, which are called parity lines, as the BL00 is used with WL0 and WL2 to access data.
As you can see from Figure 1, the advantage of a single-ended storage array over a differential storage array is the simple and neat connection of all of the wires, which reduces layout effort and simplifies the alignment of the storage cells ; The voltage in the physical circuit that can be removed by the differential pair affects one another relative to each other, that is, the voltage value within the memory cell that affects each other during access, due to the leakage current of the transistor.
Differences in specification design
In terms of the design, the DRAM chip is configured with a plurality of memory arrays. In this paper, the layout area formed by the memory arrays is named a memory array. In addition, the memory array can divide many memory blocks and aggregate the memory blocks into one Block Cluster. Regarding the DRAM chip proposed in this paper, its internal architecture is shown in FIG. 2. These memory blocks are configured with the same address space, referred to as block space, which contains a plurality of Single-ended memory array with the same data width, or multiple differential memory arrays with the same width as the half data width, there are a Hold Cell and a Refresh Cell in the figure, Active Hold, and Active Refresh. Local update jobs can be performed via parallel technology by including update controllers and column decoders within the memory block.
There are many factors that determine the Sblock, such as the frequency at which the update job is performed, the time it waits for the job to be updated, the interval at which to update the job, and the time it takes to access the job; these are referred to as the update FCrefresh, t_wait, t_refresh, and t_access. The product of the block space and the data width (W_data) is the number of bits contained in the memory block, which is named Block capacity (C_block) The relationship between these factors can be expressed by the following mathematical equations, with the following examples:
Figure 2: DRAM chip internal architecture
Differences in physical structure
In a solid structure, a single bit line connecting all memory cells on a single memory array, the length of the metal wire, and the parasitic capacitances limit the maximum block space, from the layout of the memory array and the characteristics of the memory cells These factors are illustrated in Figure 3. Figure 3 presents a physical structure to illustrate the layout of the metal wires on the die, where the side view presents a differential storage array placing those metal wires connected to + BL and -BL over the underlying metal layer, Like the first metal layer, indicated by a thick dotted line in the figure; the single-ended storage array instead places those metal wires connected to the BL on the upper metal layer, like the third metal layer, thinned in the figure Solid lines show the top view of the differential storage array will widen the metal wire to increase the parasitic capacitance; single-ended storage array but instead to use the smallest line width to remove parasitic capacitance.
Please refer to FIG. 3 below. When WL0 or WL1 turns on the transistor, the capacitor connected to it will discharge to BL or + BL or -BL. The current of the bit line is connected to the data driver through a piece of metal wire and the data is received The total capacitance of those parasitic wires in the figure is marked as 'C_BL' in the figure, which is also related to the hardware circuit that enables the writeback function; there is a test point (TP) in the figure for detecting the storage of the memory cell State, its voltage value is the storage voltage (V_storage) .When the test point of the charge gradually moved to the metal wire, the test point voltage will gradually decline, in addition, those with the bit line connected to the transistor There is a leakage current, even the output of the data driver, so the charge that is transferred to the metal wire will be taken away.If increasing the capacitance of C_BL slows the charge removal from the metal wire, however, the metal The wire needs to take more charge from the test point to accumulate enough voltage to determine the data value and in addition to increase the precharge time; this can increase the time it takes to read a job and return Write operation time. If the C_BL capacitance can approach zero to shorten the pre-charge time, but those moved to the metal wire will quickly drain the charge, and the test point voltage value will quickly return to zero; this The phenomenon, like a spike that causes the data receiver to fail to determine the data value, however, is likely to be solved by enhancing the overall performance of the data receiver.This parasitic capacitance needs to be large enough for a differential storage array Capacity to determine the data value, but for the single-ended storage array instead expect the smallest capacitance, otherwise not only need longer write-back time to restore the storage state, may also need more capacitance to maintain the time being read Data value, or even unable to judge the data value.
The maximum of the block space is proportional to the overall performance of the data receiver, proportional to the capacitance (C_storage) inside the memory cell, inversely proportional to the parasitic capacitance of the metal line, inversely proportional to the total impedance of the metal line, inversely proportional to the current path The dynamic total leakage current (i_DTLC), which means that every time a storage array is being accessed, it will dynamically change according to the storage voltage of each storage unit. Through the capacitor's charge-sharing law Calculate the value of the voltage on the bit line at the time the data is being read, that is, 'V_BL (@reading)', where the equation is as follows, where 'V_BL (@reading)' is the difference in the bit line Voltage value, 'V_precharge' is pre-charged voltage value which is 1 / 2V_dd in the differential storage array and 0:
Differences in storage voltage
The following nomenclature should be clearly defined before entering the subject of this paragraph: 'The supply voltage (V_dd)' is the supply voltage outside the memory cell, ie the supply of positive voltage towards the digital logic circuit; 'Storage voltage (V_storage ) 'Is located in the storage unit for receiving the voltage value and try to maintain its corresponding logic level to provide data values during reading;' discrimination voltage (V_discerning) 'is the data receiver during reading or updating period Can identify the limit of the data value for the slightest voltage change; 'V_margin' MIN 'is the data receiver can also identify data when it is interfered with by all kinds of noise during reading or updating period The minimum boundary voltage value of the value, the noise contains power noise and switching noise; 'minimum difference voltage (ΔV〡MIN))' is equal to the identification voltage plus the minimum noise boundary, during reading or updating can be in The minimum storage voltage that can be discriminated by the data receiver when the signal is disturbed by the noise can also affect the limit of the update time. In addition, 'cell voltage (V_cell)' is the author A method of provisioning voltage RAT Table about the proposed SRAM, which is different from the use of the stored voltage.
Figure 4 shows the differential storage array and single-ended storage array storage voltage, and highlight the difference in a single storage unit.In order to ignore different storage arrays in the access technology differences, so the voltage waveform corresponding to To the hardware circuit is a single storage unit.In other words, it is set in the same process parameters, capacitance and leakage current to compare the difference on the storage voltage.
The gate voltage of the transistor (V_t) causes the storage voltage to be lower than the supply voltage, and gradually increasing the gate voltage of the transistor allows the storage voltage to gradually approach the supply voltage. In order to remove the gate voltage, the differential storage array During the access period, the word line voltage will reach at least the supply voltage plus the gate voltage so that the maximum storage voltage equals the supply voltage. The single-ended storage array can achieve the same In addition, high gate voltage transistors can be used via multiple gate voltage process techniques, thus reducing leakage current and reducing leakage currents using the triple-well process ) To design the column decoder output driver, so that the word line can be negative voltage cut-off transistor.
The voltage waveform diagram of Figure 4 shows the operating state formed by the effect of removing the gate voltage.The stored voltage of the differential memory array reaches the precharged voltage value first before being written However, the single-ended memory array has no pre-charge voltage value, and the storage voltage of the differential memory array gradually approaches half the power supply voltage value during the retention period. However, the single-ended memory array Is gradually approaching the minimum voltage value, which is the ground voltage value.This shows that single-ended storage array update time is about twice the differential storage array.
Figure 5 shows the effect of adding a gate voltage to highlight the difference in benefits between a differential storage array and a single-ended storage array. During the write-in period, the maximum stored voltage is low At the power supply voltage, this affects the voltage symmetry of the differential storage array, and for the storage voltage of the differential storage array during the holding period, the discharging curve reaches half the power supply voltage value faster than the charging curve, so that Update time was forced to shorten, which shows that single-ended storage array update time than the differential storage array twice.
Some of the factors that can affect the time are known from the above analysis, where the leakage current is the dominant factor and proportional to the operating temperature. With regard to the tDleakage of a single cell within the differential storage array and the single-ended storage The tSleakage of a single cell within an array can be expressed by the following mathematical equation, where 't_zeroing' represents the time at which a single ended cell performs a zero reset each time the storage voltage is zero, ie, the time at which an active hold is initiated:
Since the update time of each internal memory cell is affected whenever a memory array is being accessed, the remaining memory cells are shortened by this access operation and are referred to as shrinking time. The shrink time (σtDshrink) and the single-ended storage array shrink time (σtSshrink) can be expressed by the following mathematical equations, where 't_precharge' represents the precharge time, 't_rdvwr' represents the read or write time, 't_rewrite' represents Write back time:
The dynamic update time (σt_refresh @ working) for various storage arrays in operation may be expressed by the following mathematical equation, and the dynamic update time is different from the design update time, where 'T_access' represents the number of access jobs executed:
Figure 4: Storage voltage comparison of memory cells (without Vt)
in conclusion
However, the access characteristics of the single-ended memory array are a major challenge to the design of the data receiver. Therefore, it can be inferred that the 1T1C DRAM cell The differential amplifier was used to read the data since its appearance.This paper presents a single-ended memory array based on the changes of DRAM access technology, which is based on the SRAM cell composed of triode and another resistor. In short, the static reduction technology, the same dynamic access characteristics in the standard CMOS process technology, when the number of SRAM cell transistor is reduced to three when the original features less, in particular access Different characteristics, and similar to the DRAM cell.